Slide 10
Slide 10 text
Copyright © 2014 Embecosm. Freely available under a Creative Commons license
TableGen Example
class ALU_RR subOp, string
asmstr, list pattern>
: InstRR<0x8, (outs GPR:$rD), (ins GPR:
$rA, GPR:$rB),
!strconcat(asmstr, "\t$rD, $rA, $rB"),
pattern> {
bits<5> rD; bits<5> rA; bits<5> rB;
bits<4> op;
let Inst{25-21} = rD;
let Inst{20-16} = rA;
let Inst{15-11} = rB;
let Inst{3-0} = op;
let op = subOp;
}
class ALU1_RR subOp, string
asmstr, SDNode OpNode>
: ALU_RR;
let isAsCheapAsAMove = 1 in {
def SUB : ALU1_RR<0x2, "l.sub", sub>;
let isCommutable=1 in {
def ADD : ALU1_RR<0x0, "l.add", add>;
def AND : ALU1_RR<0x3, "l.and", and>;
def OR : ALU1_RR<0x4, "l.or", or>;
def XOR : ALU1_RR<0x5, "l.xor", xor>;
}
}
class Ri num, string n> :
Register {
let Num = num;
}
def R0 : Ri< 0, "r0">, DwarfRegNum<[0]>;
def R1 : Ri< 1, "r1">, DwarfRegNum<[1]>;
def R2 : Ri< 2, "r2">, DwarfRegNum<[2]>;