ちょっと待って、Rocketは
RTLでシミュレーションしてるの?
• Rocket-ChipのシミュレーションはRTLが前提
• Chiselでシミュレーションできれば良いのだが、やり方が書いていな
い。
• そのためRTLの生成に時間がかかる (Chisel→FIR→Verilog)
• ちなみに、Chisel→VerilogのRTLは死ぬほど読みにくい。
57
wire _GEN_53; // @[Monitor.scala 64:14:
[email protected]]
wire _GEN_65; // @[Monitor.scala 73:14:
[email protected]]
wire _GEN_75; // @[Monitor.scala 81:14:
[email protected]]
wire _GEN_85; // @[Monitor.scala 89:14:
[email protected]]
wire _GEN_95; // @[Monitor.scala 97:14:
[email protected]]
wire _GEN_105; // @[Monitor.scala 105:14:
[email protected]]
plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0)) plusarg_reader ( // @[PlusArg.scala
42:11:
[email protected]]
.out(plusarg_reader_out)
);
assign _T_26 = io_in_a_bits_source <= 9'h12f; // @[Parameters.scala 55:20:
[email protected]]
assign _T_36 = 6'h7 << io_in_a_bits_size; // @[package.scala 185:77:
[email protected]]
assign _T_37 = _T_36[2:0]; // @[package.scala 185:82:
[email protected]]
assign _T_38 = ~ _T_37; // @[package.scala 185:46:
[email protected]]
assign _GEN_18 = {{14'd0}, _T_38}; // @[Edges.scala 21:16:
[email protected]]
assign _T_39 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 21:16:
[email protected]]
assign _T_40 = _T_39 == 17'h0; // @[Edges.scala 21:24:
[email protected]]
assign _T_41 = {{1'd0}, io_in_a_bits_size}; // @[Misc.scala 203:34:
[email protected]]
assign _T_42 = _T_41[1:0]; // @[OneHot.scala 51:49:
[email protected]]
assign _T_43 = 4'h1 << _T_42; // @[OneHot.scala 52:12:
[email protected]]
assign _T_44 = _T_43[2:0]; // @[OneHot.scala 52:27:
[email protected]]
assign _T_45 = _T_44 | 3'h1; // @[Misc.scala 203:81:
[email protected]]
assign _T_46 = io_in_a_bits_size >= 2'h3; // @[Misc.scala 207:21:
[email protected]]
assign _T_47 = _T_45[2]; // @[Misc.scala 210:26:
[email protected]]
assign _T_48 = io_in_a_bits_address[2]; // @[Misc.scala 211:26:
[email protected]]
assign _T_49 = _T_48 == 1'h0; // @[Misc.scala 212:20:
[email protected]]
assign _T_51 = _T_47 & _T_49; // @[Misc.scala 216:38:
[email protected]]
assign _T_52 = _T_46 | _T_51; // @[Misc.scala 216:29:
[email protected]]
assign _T_54 = _T_47 & _T_48; // @[Misc.scala 216:38:
[email protected]]
assign _T_55 = _T_46 | _T_54; // @[Misc.scala 216:29:
[email protected]]
assign _T_56 = _T_45[1]; // @[Misc.scala 210:26:
[email protected]]
assign _T_57 = io_in_a_bits_address[1]; // @[Misc.scala 211:26:
[email protected]]
assign _T_58 = _T_57 == 1'h0; // @[Misc.scala 212:20:
[email protected]]
こんなの読めますか...?
ってかECOとか
どうするんだ...