Slide 62
Slide 62 text
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©2022 Alex Blewitt
Top-down Analysis Method
USING PERFORMANCE MONITORING EVENTS
Additionally, the metric uses the UOPS_ISSUED.ANY, which is common in recent Intel microarchitec-
tures, as the denominator. The UOPS_ISSUED.ANY event counts the total number of Uops that the RAT
issues to RS.
The VectorMixRate metric gives the percentage of injected blend uops out of all uops issued. Usually a
VectorMixRate over 5% is worth investigating.
VectorMixRate[%] = 100 * UOPS_ISSUED.VECTOR_WIDTH_MISMATCH / UOPS_ISSUED.ANY
Note the actual penalty may vary as it stems from the additional data-dependency on the destination
register the injected blend operations add.
B.2 PERFORMANCE MONITORING AND MICROARCHITECTURE
This section provides information of performance monitoring hardware and terminology related to the
Silvermont, Airmont and Goldmont microarchitectures. The features described here may be specific to
individual microarchitecture, as indicated in Table B-1.
Figure B-3. TMAM Hierarchy Supported by Skylake Microarchitecture
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USING PERFORMANCE MONITORING EVENTS
The single entry point of division at a pipeline’s issue-stage (allocation-stage) makes the four categories
additive to the total possible slots. The classification at slots granularity (sub-cycle) makes the break-
down very accurate and robust for superscalar cores, which is a necessity at the top-level.
Figure B-2. TMAM’s Top Level Drill Down Flowchart
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https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-optimization-reference-manual
Ahmed Yasin