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WebCore: Architectural Support for Mobile Web Browsing Yuhao Zhu, Vijay Janapa Reddi Department of Electrical and Computer Engineering The University of Texas at Austin ISCA MainTalk — June 18th, 2014

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Swift

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The Fundamental Challenges 4

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The Fundamental Challenges 4 Achieving High Performance Demanded by End-User

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The Fundamental Challenges 4 Achieving High Performance Demanded by End-User Conserving Energy Due to Limited Battery Capacity

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The Fundamental Challenges 4 Achieving High Performance Demanded by End-User Conserving Energy Due to Limited Battery Capacity Conflicting requirements

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The Fundamental Challenges How to achieve high performance with low energy? 4 Achieving High Performance Demanded by End-User Conserving Energy Due to Limited Battery Capacity Conflicting requirements

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The Fundamental Challenges How to achieve high performance with low energy? 4 Achieving High Performance Demanded by End-User Conserving Energy Due to Limited Battery Capacity Conflicting requirements A mobile architecture

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The Fundamental Challenges How to achieve high performance with low energy? 4 Achieving High Performance Demanded by End-User Conserving Energy Due to Limited Battery Capacity Conflicting requirements A mobile architecture WebCore:

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Executive Summary 5 Time Energy General Purpose Designs

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Executive Summary 5 Time Energy General Purpose Designs Diminishing return

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Executive Summary 5 Time Energy General Purpose Designs ASIC?

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Executive Summary 5 Time Energy General Purpose Designs ASIC? Extremely challenging ‣Chrome: 7M LoC, 29 languages ‣Firefox: 10M LoC, 33 languages

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Executive Summary 5 Time Energy General Purpose Designs ASIC?

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Executive Summary 5 Time Energy General Purpose Designs ASIC? WebCore Goal

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Executive Summary 5 Time Energy General Purpose Designs ??? ASIC? WebCore Goal

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Executive Summary 6 Time Energy General Purpose Designs WebCore Goal

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Executive Summary 6 Time Energy General Purpose Designs WebCore Goal

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Executive Summary 6 Time Energy General Purpose Designs Customizing µarch Parameters WebCore Goal

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Executive Summary 6 Time Energy General Purpose Designs Customizing µarch Parameters Specialized FU and Memory WebCore Goal

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Agenda of Today’s Talk ▸Motivation of our work: energy-efficiency of the mobile Web 7

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Agenda of Today’s Talk ▸Motivation of our work: energy-efficiency of the mobile Web ▸How does WebCore improve the energy-efficiency? ▹Customization ▹Specialization 7

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Agenda of Today’s Talk ▸Motivation of our work: energy-efficiency of the mobile Web ▸How does WebCore improve the energy-efficiency? ▹Customization ▹Specialization ▸Evaluation Results 7

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Agenda of Today’s Talk ▸Motivation of our work: energy-efficiency of the mobile Web ▸How does WebCore improve the energy-efficiency? ▹Customization ▹Specialization ▸Evaluation Results ▸Related Work 7

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Agenda of Today’s Talk ▸Motivation of our work: energy-efficiency of the mobile Web ▸How does WebCore improve the energy-efficiency? ▹Customization ▹Specialization ▸Evaluation Results ▸Related Work 8

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Customization: Find the Ideal General Purpose Baseline Architecture

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▸Why customization?!? Customization: Find the Ideal General Purpose Baseline Architecture

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▸Why customization?!? ▸What is a proper general purpose baseline architecture? Customization: Find the Ideal General Purpose Baseline Architecture

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▸Why customization?!? ▸What is a proper general purpose baseline architecture? ▹Out-of-order (Silvermont, A15) or in-order (Saltwell, A7)? Customization: Find the Ideal General Purpose Baseline Architecture

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▸Why customization?!? ▸What is a proper general purpose baseline architecture? ▹Out-of-order (Silvermont, A15) or in-order (Saltwell, A7)? ▹Are existing general purpose mobile designs ideal? Customization: Find the Ideal General Purpose Baseline Architecture

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▸Why customization?!? ▸What is a proper general purpose baseline architecture? ▹Out-of-order (Silvermont, A15) or in-order (Saltwell, A7)? ▹Are existing general purpose mobile designs ideal? ▸Exhaustive design space exploration Customization: Find the Ideal General Purpose Baseline Architecture

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▸Why customization?!? ▸What is a proper general purpose baseline architecture? ▹Out-of-order (Silvermont, A15) or in-order (Saltwell, A7)? ▹Are existing general purpose mobile designs ideal? ▸Exhaustive design space exploration Customization: Find the Ideal General Purpose Baseline Architecture

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▸Why customization?!? ▸What is a proper general purpose baseline architecture? ▹Out-of-order (Silvermont, A15) or in-order (Saltwell, A7)? ▹Are existing general purpose mobile designs ideal? ▸Exhaustive design space exploration Customization: Find the Ideal General Purpose Baseline Architecture

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Design Space Exploration (DSE) Setup ▸Integrated power (McPAT) and performance x86 full-system simulator (Marss86) ▸WebKit engine in the Chromium Web browser 10

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Design Space Exploration (DSE) Setup ▸Integrated power (McPAT) and performance x86 full-system simulator (Marss86) ▸WebKit engine in the Chromium Web browser 10

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Design Space Exploration (DSE) Setup 11 ▸Webpages selection using PCA

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▹PCs calculated from webpage-inherent and µarch-dependent features (~400 in total) Design Space Exploration (DSE) Setup 11 ▸Webpages selection using PCA

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▹PCs calculated from webpage-inherent and µarch-dependent features (~400 in total) Design Space Exploration (DSE) Setup 11 ▸Webpages selection using PCA 10-4 10-3 10-2 10-1 100 101 PC2 (log) -5 0 5 PC1

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▹PCs calculated from webpage-inherent and µarch-dependent features (~400 in total) ▹PCs calculated from webpage-inherent and µarch-dependent features (~400 in total) Design Space Exploration (DSE) Setup 11 ▸Webpages selection using PCA 10-4 10-3 10-2 10-1 100 101 PC2 (log) -5 0 5 PC1 dominated by # webpage elements

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▹PCs calculated from webpage-inherent and µarch-dependent features (~400 in total) ▹PCs calculated from webpage-inherent and µarch-dependent features (~400 in total) ▹PCs calculated from webpage-inherent and µarch-dependent features (~400 in total) Design Space Exploration (DSE) Setup 11 ▸Webpages selection using PCA 10-4 10-3 10-2 10-1 100 101 PC2 (log) -5 0 5 PC1 dominated by IPC

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▹PCs calculated from webpage-inherent and µarch-dependent features (~400 in total) 10-4 10-3 10-2 10-1 100 101 PC2 (log) -5 0 5 PC1 Design Space Exploration (DSE) Setup 11 ▸Webpages selection using PCA

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Design Space Exploration (DSE) Findings 12

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Design Space Exploration (DSE) Findings 12

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Design Space Exploration (DSE) Findings 12

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Design Space Exploration (DSE) Findings ▸Out-of-order µarchitecture is much more flexible 12

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Design Space Exploration (DSE) Findings ▸Out-of-order µarchitecture is much more flexible 12

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Design Space Exploration (DSE) Findings ▸Out-of-order µarchitecture is much more flexible 12 ▸In-order cores are acceptable if end-users can tolerate latency

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Understand the Difference Using Kernel Knowledge 13

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Understand the Difference Using Kernel Knowledge 13 Execution time breakdown

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Understand the Difference Using Kernel Knowledge In-order design 13

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Understand the Difference Using Kernel Knowledge In-order design 13

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▸In-order designs show strong kernel variance Understand the Difference Using Kernel Knowledge In-order design 13

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▸In-order designs show strong kernel variance Understand the Difference Using Kernel Knowledge In-order design 13

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▸In-order designs show strong kernel variance Understand the Difference Using Kernel Knowledge In-order design 13

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▸In-order designs show strong kernel variance Understand the Difference Using Kernel Knowledge In-order design 13 Out-of-order design

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▸In-order designs show strong kernel variance Understand the Difference Using Kernel Knowledge In-order design 13 Out-of-order design ▸An Out-of-order design can accommodate kernel variance

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14 Customization: Identifying Major Sources of Energy Inefficiency

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14 P2 P1 Customization: Identifying Major Sources of Energy Inefficiency

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14 Customization: Identifying Major Sources of Energy Inefficiency P1 P2 ARM A15 Issue width 1 3 3 # Function units 2 3 8 Load queue size 4 16 16 Store queue size 4 16 16 BTB size 1024 128 256 ROB size 128 128 40+ L1 I-$ size (KB) 64 128 32 # Physical registers 128 140 ? L1 D-$ size (KB) 8 64 32 L2-$ size (KB) 256 1024 <4096

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P1 P2 ARM A15 Issue width 1 3 3 # Function units 2 3 8 Load queue size 4 16 16 Store queue size 4 16 16 BTB size 1024 128 256 ROB size 128 128 40+ L1 I-$ size (KB) 64 128 32 # Physical registers 128 140 ? L1 D-$ size (KB) 8 64 32 L2-$ size (KB) 256 1024 <4096 15 P2 P1 Customization: Identifying Major Sources of Energy Inefficiency

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P1 P2 ARM A15 Issue width 1 3 3 # Function units 2 3 8 Load queue size 4 16 16 Store queue size 4 16 16 BTB size 1024 128 256 ROB size 128 128 40+ L1 I-$ size (KB) 64 128 32 # Physical registers 128 140 ? L1 D-$ size (KB) 8 64 32 L2-$ size (KB) 256 1024 <4096 15 P2 P1 Customization: Identifying Major Sources of Energy Inefficiency

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P1 P2 ARM A15 Issue width 1 3 3 # Function units 2 3 8 Load queue size 4 16 16 Store queue size 4 16 16 BTB size 1024 128 256 ROB size 128 128 40+ L1 I-$ size (KB) 64 128 32 # Physical registers 128 140 ? L1 D-$ size (KB) 8 64 32 L2-$ size (KB) 256 1024 <4096 15 P2 P1 Customization: Identifying Major Sources of Energy Inefficiency

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P1 P2 ARM A15 Issue width 1 3 3 # Function units 2 3 8 Load queue size 4 16 16 Store queue size 4 16 16 BTB size 1024 128 256 ROB size 128 128 40+ L1 I-$ size (KB) 64 128 32 # Physical registers 128 140 ? L1 D-$ size (KB) 8 64 32 L2-$ size (KB) 256 1024 <4096 ▸Instruction delivery 15 P2 P1 Customization: Identifying Major Sources of Energy Inefficiency

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P1 P2 ARM A15 Issue width 1 3 3 # Function units 2 3 8 Load queue size 4 16 16 Store queue size 4 16 16 BTB size 1024 128 256 ROB size 128 128 40+ L1 I-$ size (KB) 64 128 32 # Physical registers 128 140 ? L1 D-$ size (KB) 8 64 32 L2-$ size (KB) 256 1024 <4096 ▸Instruction delivery 15 P2 P1 Customization: Identifying Major Sources of Energy Inefficiency

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P1 P2 ARM A15 Issue width 1 3 3 # Function units 2 3 8 Load queue size 4 16 16 Store queue size 4 16 16 BTB size 1024 128 256 ROB size 128 128 40+ L1 I-$ size (KB) 64 128 32 # Physical registers 128 140 ? L1 D-$ size (KB) 8 64 32 L2-$ size (KB) 256 1024 <4096 ▸Instruction delivery ▸Data feeding 15 P2 P1 Customization: Identifying Major Sources of Energy Inefficiency

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Agenda of Today’s Talk ▸Motivation of our work: energy-efficiency of the mobile Web ▸How does WebCore improve the energy-efficiency? ▹Customization ▹Specialization -Mitigate instruction delivery: Style resolution unit (SRU) -Improving data feeding: Browser engine cache ▸Evaluation Results ▸Related Work 16

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WebCore Specialization Overview 17 Customized core IF ID EX MEM WB Hardware Layer

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WebCore Specialization Overview 17 Customized core IF ID MEM WB ALU MUL FPU Hardware Layer

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WebCore Specialization Overview 17 Customized core IF ID MEM WB ALU MUL FPU SRU Hardware Layer

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L1 D-cache WebCore Specialization Overview 17 Customized core IF ID MEM WB ALU MUL FPU SRU Hardware Layer

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L1 D-cache WebCore Specialization Overview 17 Customized core IF ID MEM WB ALU MUL FPU SRU Hardware Layer Browser Engine Cache

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L1 D-cache WebCore Specialization Overview 17 Customized core IF ID MEM WB ALU MUL FPU SRU Hardware Layer API Layer Browser Engine Cache

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L1 D-cache WebCore Specialization Overview 17 Customized core IF ID MEM WB ALU MUL FPU SRU Style_apply(Id); Hardware Layer API Layer Browser Engine Cache

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DOM_LD(Id, &attr); DOM_ST(Id, &attr); L1 D-cache WebCore Specialization Overview 17 Customized core IF ID MEM WB ALU MUL FPU SRU Style_apply(Id); Hardware Layer API Layer Browser Engine Cache

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DOM_LD(Id, &attr); DOM_ST(Id, &attr); L1 D-cache WebCore Specialization Overview 17 Customized core IF ID MEM WB ALU MUL FPU SRU Style_apply(Id); Hardware Layer API Layer Runtime Layer Browser Engine Cache

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DOM_LD(Id, &attr); DOM_ST(Id, &attr); L1 D-cache WebCore Specialization Overview 17 Customized core IF ID MEM WB ALU MUL FPU SRU Style_apply(Id); Hardware Layer API Layer Runtime Layer Cache Management Browser Engine Cache

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DOM_LD(Id, &attr); DOM_ST(Id, &attr); L1 D-cache WebCore Specialization Overview 17 Customized core IF ID MEM WB ALU MUL FPU SRU Style_apply(Id); Hardware Layer API Layer Runtime Layer Cache Management SRU Access Browser Engine Cache

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DOM_LD(Id, &attr); DOM_ST(Id, &attr); L1 D-cache WebCore Specialization Overview 17 Customized core IF ID MEM WB ALU MUL FPU SRU Style_apply(Id); Hardware Layer API Layer Runtime Layer Cache Management Software Failsafe SRU Access Browser Engine Cache

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Agenda of Today’s Talk ▸Motivation of our work: energy-efficiency of the mobile Web ▸How does WebCore improve the energy-efficiency? ▹Customization ▹Specialization -Mitigate instruction delivery: Style resolution unit (SRU) -Improving data feeding: Browser engine cache ▸Evaluation Results ▸Related Work 18

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▸Style kernel is the most critical kernel Style Resolution Unit 19

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▸Style kernel is the most critical kernel Style Resolution Unit 19 Execution time breakdown Energy consumption breakdown

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▸Style kernel is the most critical kernel Style Resolution Unit 19 for (each rule in matchedRules) { for (each property in rule) { switch (property.id) { case Font: Style[Font] = Handler(property.value, DOMNode); break; case N: ...}}}

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▸Style kernel is the most critical kernel Style Resolution Unit 19 for (each rule in matchedRules) { for (each property in rule) { switch (property.id) { case Font: Style[Font] = Handler(property.value, DOMNode); break; case N: ...}}}

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▸Style kernel is the most critical kernel Style Resolution Unit 19 for (each rule in matchedRules) { for (each property in rule) { switch (property.id) { case Font: Style[Font] = Handler(property.value, DOMNode); break; case N: ...}}} Rule-level Parallelism (RLP)

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▸Style kernel is the most critical kernel Style Resolution Unit 19 for (each rule in matchedRules) { for (each property in rule) { switch (property.id) { case Font: Style[Font] = Handler(property.value, DOMNode); break; case N: ...}}} Rule-level Parallelism (RLP)

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▸Style kernel is the most critical kernel Style Resolution Unit 19 for (each rule in matchedRules) { for (each property in rule) { switch (property.id) { case Font: Style[Font] = Handler(property.value, DOMNode); break; case N: ...}}} Rule-level Parallelism (RLP) Property-level Parallelism (PLP)

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▸Style kernel is the most critical kernel Style Resolution Unit 19 for (each rule in matchedRules) { for (each property in rule) { switch (property.id) { case Font: Style[Font] = Handler(property.value, DOMNode); break; case N: ...}}} Rule-level Parallelism (RLP) Property-level Parallelism (PLP) ▸Exploiting the parallelism to increase the arithmetic intensity and reduce instruction footprint

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▸A running example from www.cnn.com Style Resolution Unit (2) Rule Property 1 Property 1 Property 2 Property 2 Rule id value id value 1 padding 0 margin 0 2 padding 6 px width 36 px Style Rules padding 0 width 6 px 36 px margin 0

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▸A running example from www.cnn.com Style Resolution Unit (2) Rule Property 1 Property 1 Property 2 Property 2 Rule id value id value 1 padding 0 margin 0 2 padding 6 px width 36 px Style Rules padding 0 width 6 px 36 px margin 0 High priority

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Property 1 Property 1 Property 2 Property 2 Property 3 Property 3 id value id value id value Final Style Info ▸A running example from www.cnn.com Style Resolution Unit (2) Rule Property 1 Property 1 Property 2 Property 2 Rule id value id value 1 padding 0 margin 0 2 padding 6 px width 36 px Style Rules padding 0 width 6 px 36 px margin 0 High priority

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Property 1 Property 1 Property 2 Property 2 Property 3 Property 3 id value id value id value Final Style Info ▸A running example from www.cnn.com Style Resolution Unit (2) Rule Property 1 Property 1 Property 2 Property 2 Rule id value id value 1 padding 0 margin 0 2 padding 6 px width 36 px Style Rules padding 0 width 6 px 36 px margin 0 High priority

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Property 1 Property 1 Property 2 Property 2 Property 3 Property 3 id value id value id value Final Style Info ▸A running example from www.cnn.com Style Resolution Unit (2) Rule Property 1 Property 1 Property 2 Property 2 Rule id value id value 1 padding 0 margin 0 2 padding 6 px width 36 px Style Rules padding 0 width 6 px 36 px margin 0 High priority

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Property 1 Property 1 Property 2 Property 2 Property 3 Property 3 id value id value id value Final Style Info ▸A running example from www.cnn.com Style Resolution Unit (2) Rule Property 1 Property 1 Property 2 Property 2 Rule id value id value 1 padding 0 margin 0 2 padding 6 px width 36 px Style Rules padding 0 width 6 px 36 px margin 0 High priority

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Property 1 Property 1 Property 2 Property 2 Property 3 Property 3 id value id value id value Final Style Info ▸A running example from www.cnn.com Style Resolution Unit (2) Rule Property 1 Property 1 Property 2 Property 2 Rule id value id value 1 padding 0 margin 0 2 padding 6 px width 36 px Style Rules padding 0 width 6 px 36 px margin 0 High priority

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Property 1 Property 1 Property 2 Property 2 Property 3 Property 3 id value id value id value Final Style Info ▸A running example from www.cnn.com Style Resolution Unit (2) Rule Property 1 Property 1 Property 2 Property 2 Rule id value id value 1 padding 0 margin 0 2 padding 6 px width 36 px Style Rules padding 0 width 6 px 36 px margin 0 High priority

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Property 1 Property 1 Property 2 Property 2 Property 3 Property 3 id value id value id value Final Style Info ▸A running example from www.cnn.com Style Resolution Unit (2) Rule Property 1 Property 1 Property 2 Property 2 Rule id value id value 1 padding 0 margin 0 2 padding 6 px width 36 px Style Rules padding 0 width 6 px 36 px ▸Order Matters in RLP ▸Order Does Not Matter in PLP margin 0 High priority

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Property 1 Property 1 Property 2 Property 2 Property 3 Property 3 id value id value id value Final Style Info ▸A running example from www.cnn.com Style Resolution Unit (2) Rule Property 1 Property 1 Property 2 Property 2 Rule id value id value 1 padding 0 margin 0 2 padding 6 px width 36 px Style Rules padding 0 width 6 px 36 px ▸Order Matters in RLP ▸Order Does Not Matter in PLP margin 0 High priority

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Property 1 Property 1 Property 2 Property 2 Property 3 Property 3 id value id value id value Final Style Info ▸A running example from www.cnn.com Style Resolution Unit (2) Rule Property 1 Property 1 Property 2 Property 2 Rule id value id value 1 padding 0 margin 0 2 padding 6 px width 36 px Style Rules padding 0 width 6 px 36 px ▸Order Matters in RLP ▸Order Does Not Matter in PLP margin 0 High priority

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... ... Rule j ... ... Prop l ... ... Rule i.id ... Prop m ... Prop k ... Rule j.id ... ... ... ... ... start end start end Rule i Prop k Prop m Prop m Prop l Style l Style m Style k Style Resolution Unit (3) 21 ▸Order Matters in RLP ▸Order Does Not Matter in PLP

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... ... Rule j ... ... Prop l ... ... Rule i.id ... Prop m ... Prop k ... Rule j.id ... ... ... ... ... start end start end Rule i Prop k Prop m Prop m Prop l Style l Style m Style k Style Resolution Unit (3) 21 Input Scratchpad Memory ▸Order Matters in RLP ▸Order Does Not Matter in PLP

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... ... Rule j ... ... Prop l ... ... Rule i.id ... Prop m ... Prop k ... Rule j.id ... ... ... ... ... start end start end Rule i Prop k Prop m Prop m Prop l Style l Style m Style k Style Resolution Unit (3) 21 Input Scratchpad Memory ▸Order Matters in RLP ▸Order Does Not Matter in PLP Higher Priority

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... ... Rule j ... ... Prop l ... ... Rule i.id ... Prop m ... Prop k ... Rule j.id ... ... ... ... ... start end start end Rule i Prop k Prop m Prop m Prop l Style l Style m Style k Style Resolution Unit (3) 21 Input Scratchpad Memory Conflict Resolution ▸Order Matters in RLP ▸Order Does Not Matter in PLP Higher Priority

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... ... Rule j ... ... Prop l ... ... Rule i.id ... Prop m ... Prop k ... Rule j.id ... ... ... ... ... start end start end Rule i Prop k Prop m Prop m Prop l Style l Style m Style k Style Resolution Unit (3) 21 Input Scratchpad Memory Conflict Resolution ▸Order Matters in RLP ▸Order Does Not Matter in PLP Higher Priority Prop m Prop m

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... ... Rule j ... ... Prop l ... ... Rule i.id ... Prop m ... Prop k ... Rule j.id ... ... ... ... ... start end start end Rule i Prop k Prop m Prop m Prop l Style l Style m Style k Style Resolution Unit (3) 21 Input Scratchpad Memory Conflict Resolution ▸Order Matters in RLP ▸Order Does Not Matter in PLP Higher Priority Prop m

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... ... Rule j ... ... Prop l ... ... Rule i.id ... Prop m ... Prop k ... Rule j.id ... ... ... ... ... start end start end Rule i Prop k Prop m Prop m Prop l Style l Style m Style k Style Resolution Unit (3) 21 Input Scratchpad Memory Conflict Resolution Compute Lanes ▸Order Matters in RLP ▸Order Does Not Matter in PLP Higher Priority

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... ... Rule j ... ... Prop l ... ... Rule i.id ... Prop m ... Prop k ... Rule j.id ... ... ... ... ... start end start end Rule i Prop k Prop m Prop m Prop l Style l Style m Style k Style Resolution Unit (3) 21 Input Scratchpad Memory Output Scratchpad Memory Conflict Resolution Compute Lanes ▸Order Matters in RLP ▸Order Does Not Matter in PLP Higher Priority

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Agenda of Today’s Talk ▸Motivation of our work: energy-efficiency of the mobile Web ▸How does WebCore improve the energy-efficiency? ▹Customization ▹Specialization ▸Evaluation Results ▸Related Work 22

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Evaluations 23 ▸Fully synthesized using Synopsys 28 nm toolchain

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Evaluations 23 ▸Fully synthesized using Synopsys 28 nm toolchain ▸24 representative webpages

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Evaluations 23 ▸Fully synthesized using Synopsys 28 nm toolchain ▸24 representative webpages www.amazon.com www.cnn.com www.msn.com www.google.com.hk www.twitter.com www.espn.go.com www.bbc.co.uk www.slashdot.org www.youtube.com www.ebay.com www.sina.com.cn www.163.com Desktop and mobile versions

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Evaluations 24 0.55 0.688 0.825 0.963 1.1 1.6 1.8 2 2.2 2.4 Energy (J) Load Time (s)

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Evaluations 24 0.55 0.688 0.825 0.963 1.1 1.6 1.8 2 2.2 2.4 Energy (J) Load Time (s) A15-like design

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Evaluations 24 0.55 0.688 0.825 0.963 1.1 1.6 1.8 2 2.2 2.4 Energy (J) Load Time (s) A15-like design Customization

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Evaluations 24 0.55 0.688 0.825 0.963 1.1 1.6 1.8 2 2.2 2.4 Energy (J) Load Time (s) 18.6% A15-like design Customization

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Evaluations 24 0.55 0.688 0.825 0.963 1.1 1.6 1.8 2 2.2 2.4 Energy (J) Load Time (s) 18.6% 22.2% A15-like design Customization

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Evaluations 24 0.55 0.688 0.825 0.963 1.1 1.6 1.8 2 2.2 2.4 Energy (J) Load Time (s) 18.6% 22.2% A15-like design Customization Specialization

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Evaluations 24 0.55 0.688 0.825 0.963 1.1 1.6 1.8 2 2.2 2.4 Energy (J) Load Time (s) 18.6% 22.2% 22.2% A15-like design Customization Specialization

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Evaluations 24 0.55 0.688 0.825 0.963 1.1 1.6 1.8 2 2.2 2.4 Energy (J) Load Time (s) 18.6% 22.2% 9.2% 22.2% A15-like design Customization Specialization

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Evaluations 24 0.55 0.688 0.825 0.963 1.1 1.6 1.8 2 2.2 2.4 Energy (J) Load Time (s) A15-like design Customization Specialization 29.2% 47.0%

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Evaluations 25 0.55 0.688 0.825 0.963 1.1 1.6 1.8 2 2.2 2.4 Energy (J) Load Time (s) A15-like design Customization Specialization Cost of specialization: 0.59 mm2 area overhead

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Evaluations 25 0.55 0.688 0.825 0.963 1.1 1.6 1.8 2 2.2 2.4 Energy (J) Load Time (s) A15-like design Customization Specialization Cost of specialization: 0.59 mm2 area overhead Better than scaling- up approaches

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Evaluations 25 0.55 0.688 0.825 0.963 1.1 1.6 1.8 2 2.2 2.4 Energy (J) Load Time (s) A15-like design Customization Specialization Cost of specialization: 0.59 mm2 area overhead Better than scaling- up approaches I$

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Evaluations 25 0.55 0.688 0.825 0.963 1.1 1.6 1.8 2 2.2 2.4 Energy (J) Load Time (s) A15-like design Customization Specialization Cost of specialization: 0.59 mm2 area overhead Better than scaling- up approaches D$

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Evaluations 25 0.55 0.688 0.825 0.963 1.1 1.6 1.8 2 2.2 2.4 Energy (J) Load Time (s) A15-like design Customization Specialization Cost of specialization: 0.59 mm2 area overhead Better than scaling- up approaches I+D$

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Related Work 26 Hardware Software Focus on Performance Focus on Energy-Efficiency

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Related Work 26 Hardware Software Focus on Performance Focus on Energy-Efficiency Parallelization Algorithm- level Zoomm Mozilla Servo

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Related Work 26 Hardware Software Focus on Performance Focus on Energy-Efficiency Parallelization Algorithm- level Zoomm Mozilla Servo System- level Optimizations Redundancy Removal Prefetching Big/little Scheduling

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Related Work 26 Hardware Software Focus on Performance Focus on Energy-Efficiency Parallelization Algorithm- level Zoomm Mozilla Servo ASIC Tegra 4 WebRTC accelerator SiChrome System- level Optimizations Redundancy Removal Prefetching Big/little Scheduling

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Related Work 26 Hardware Software Focus on Performance Focus on Energy-Efficiency Parallelization Algorithm- level Zoomm Mozilla Servo ASIC Tegra 4 WebRTC accelerator SiChrome System- level Optimizations Redundancy Removal Prefetching Big/little Scheduling WebCore

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Conclusions 27 The Web browser has become a general purpose platform that supports a wide range of mobile Web applications Customization allows us to find the ideal general-purpose baseline architecture Hardware/software collaborative specialization leverages application knowledge to mitigate inefficiencies in general-purpose architectures

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Thank you