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28.7: A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR
ADC in 28nm CMOS with Digital Amplifier Technique
© 2017 IEEE
International Solid-State Circuits Conference 1 of 50
A 0.7V 12b 160MS/s 12.8fJ/conv-
step Pipelined-SAR ADC in 28nm
CMOS with Digital Amplifier
Technique
Kentaro Yoshioka, Tomohiko Sugimoto,
Naoya Waki, Sinnyoung Kim, Daisuke Kurose,
Hirotomo Ishii, Masanori Furuta,
Akihide Sai and Tetsuro Itakura
Toshiba Corporation, Kawasaki, Japan