20230901_KOBETA방송기술교육원_광주지역교육.pdf

Slide 1

Slide 1 text

ATSC 3.0 혁신서비스 동향 SFN 방송망 설계/관리 및 심층 Q&A 2023.09.01.(금) 14:00 ~ 15:20 KBS 미디어송출부 전성호 팀장 Korean BroadcastingSystem | Department of MediaTransmission 방송기술교육원 2023 전남권 지역 방송기술 교육 @ KBC 광주방송 4층 대강당

Slide 153

Slide 153 text

▪ Transmitter Center Frequency shall be maintained at the nominal Center Frequency ±0.5Hz, with a long-term-averaged error of zero [A/324] 153 Oscillators available for Meinberg GPS Receivers / Time Servers: TCXO, OCXO, Rubidium TCXO OCXO LQ OCXO SQ OCXO MQ OCXO HQ OCXO DHQ Rubidium (only available for 3U models) short term stability (τ = 1 sec) 2·10-9 1·10-9 5·10-10 2·10-10 5·10-12 2·10-12 2·10-11 accuracy of PPS (pulse per sec) < ±100 ns < ±100 ns < ±50 ns < ±50 ns < ±50 ns < ±50 ns < ±50 ns phase noise 1Hz -60dBc/Hz 10Hz -90dBc/Hz 100Hz -120dBc/Hz 1kHz -130dBc/Hz 1Hz -60dBc/Hz 10Hz -90dBc/Hz 100Hz -120dBc/Hz 1kHz -130dBc/Hz 1Hz -70dBc/Hz 10Hz -105dBc/Hz 100Hz -125dBc/Hz 1kHz -140dBc/Hz 1Hz -75dBc/Hz 10Hz -110dBc/Hz 100Hz -130dBc/Hz 1kHz -140dBc/Hz 1Hz < -85dBc/Hz 10Hz < -115dBc/Hz 100Hz < -130dBc/Hz 1kHz < -140dBc/Hz 1Hz < -80dBc/Hz 10Hz < -110dBc/Hz 100Hz < -125dBc/Hz 1kHz < -135dBc/Hz 1Hz -75dBc/Hz 10Hz -89dBc/Hz 100Hz -128dBc/Hz 1kHz -140dBc/Hz accuracy free run, one day ±1·10-7 ±1Hz (Note1) ±2·10-8 ±0.2Hz (Note1) ±5·10-9 ±50mHz (Note1) ±1.5·10-9 ±15mHz (Note1) ±5·10-10 ±5mHz (Note1) ±1·10-10 ±1mHz (Note1) ±2·10-11 ±0.2mHz (Note1) accuracy, free run, 1 year ±1·10-6 ±10Hz (Note1) ±4·10-7 ±4Hz (Note1) ±2·10-7 ±2Hz (Note1) ±1·10-7 ±1Hz (Note1) ±5·10-8 ±0.5Hz (Note1) ±1·10-8 ±0.1Hz (Note1) ±5·10-10 ±5mHz (Note1) accuracy GPS-synchronous, average 24h ±1·10-11 ±1·10-11 ±1·10-11 ±5·10-12 ±1·10-12 ±1·10-12 ±1·10-12 accuracy of tim e free run, 1 day ± 4.3 ms ± 865 µs ± 220 µs ± 65 µs ± 22 µs ± 4.5 µs ± 1.1 µs accuracy of tim e free run, 7 days ± 128 ms ± 32 ms ± 9.2 ms ± 2.9 ms ± 1.0 ms ± 204 µs ± 34 µs accuracy of tim e free run, 30 days ± 1.1 s ± 330 ms ± 120 ms ± 44 ms ± 16 ms ± 3.3 ms ± 370 µs accuracy of tim e free run, 1 year ± 16 s ± 6.3 s ± 4.7 s ± 1.6 s ± 788 ms ± 158 ms ± 8 ms temperature depandant drift f r ee ±1·10-6 (-20...70°C) ±2·10-7 (0...60°C) ±1·10-7 (-10...70°C) ±5·10-8 (-20...70°C) ±1·10-8 (5...70°C) ±2·10-10 (5...70°C) ±6·10-10 (-25...70°C) Oscillator Optio n s SFN 유지를 위해서는 반드시 GPS에 Locking 되어 있어야 한다.

Slide 157

Slide 157 text

✓ MND ≥ 실제 네트워크 딜레이 + 송신기 프로세싱 딜레이 : RF OK ✓ MND < 실제 네트워크 딜레이 + 송신기 프로세싱 딜레이 : RF Mute 송신기 2 프로세싱 딜레이 버퍼 시간 실제 네트워크 딜레이 2 송신기 1 프로세싱 딜레이 버퍼 시간 실제 네트워크 딜레이 1 Network 1 Network 2 Transmitter 1 Transmitter 2 Packet Release Time Bootstrap Emission Time • • • Packet 3 Packet 2 Packet 1 Packet N BGW 시그널링 39 num_emission_tim 6 uimsbf num_xmtrs_in_group 6 uimsbf xmtr_group_num 7 uimsbf maj_log_override 3 bslbf num_miso_filt_codes 2 bslbf tx_carrier_offset 2 tcimsbf reserved 6 for (i=0; i<6; i++) ‘1’ } Bootstrap_Timing_Data () { for (i=0; i<=num_emission_tim; i++) seconds 32 uimsbf nanoseconds 32 uimsbf } } Per_Transmitter_Data () { for (i=0; i<=num_xmtrs_in_group; i++) { xmtr_id 13 uimsbf tx_time_offset 16 tcimsbf txid_injection_lvl 4 uimsbf miso_filt_code_index 2 bslbf reserved 29 for (i=0; i<29; i++) ‘1’ } } Packet_Release_Time () { pkt_rls_seconds 4 uimsbf pkt_rls_a-milliseconds 10 uimsbf reserved 2 ‘11’ } Error_Check_Data () { crc16 16 uimsbf } } ATSC 3.0 Broadcast Gateway 2018 Scheduler / Studio to Transmitter Link 5 January 2018 Table 8.3 Timing and Management Stream Packet Payload Syntax No. of Bits Format Timing & Management_Packet (TMP) () { Structure_Data () { length 16 uimsbf version_major 4 uimsbf version_minor 4 uimsbf maj_log_rep_cnt_pre 4 uimsbf maj_log_rep_cnt_tim 4 uimsbf bootstrap_major 4 uimsbf bootstrap_minor 4 uimsbf min_time_to_next 5 uimsbf system_bandwidth 2 uimsbf bsr_coefficient 7 uimsbf preamble_structure 8 uimsbf ea_wakeup 2 bslbf num_emission_tim 6 uimsbf num_xmtrs_in_group 6 uimsbf xmtr_group_num 7 uimsbf maj_log_override 3 bslbf num_miso_filt_codes 2 bslbf tx_carrier_offset 2 tcimsbf reserved 6 for (i=0; i<6; i++) ‘1’ } Bootstrap_Timing_Data () { for (i=0; i<=num_emission_tim; i++) seconds 32 uimsbf nanoseconds 32 uimsbf } } Per_Transmitter_Data () { Exciter 시그널링 ATSC 3.0 Exciter • • • Frame 3 Frame 2 Frame 1 Frame N ATSC S32-230r72 Revision o 9.3 Syntax and Semantics for L1-Detail D The syntax and field semantics of the L1 following subsections. The names of sign Table 9.8 L1-De Syntax L1_Detail_signaling() { L1D_version L1D_num_rf for (L1D_rf_id=1 .. L1D_num_rf) { L1D_bonded_bsid reserved } if (L1B_time_info_flag != 00) { L1D_time_sec L1D_time_msec if (L1B_time_info_flag != 01) { L1D_time_usec if (L1B_time_info_flag != 10) { L1D_time_nsec } } } for (i=0 .. L1B_num_subframes) { if (i > 0) { Maximum Network Delay (MND) 네트워크 딜레이 계산: 장시간 관찰 결과, ‘평균치±2ms’ 이내 유지하면 정상 Instantaneous Network Delay = Current_GPS_Time() – Packet_Release_Time() 단, Network Delay 측정을 위해서는 GPS(또는 PTP)에 동기화된 장치 필요 = Bootstrap_Timing_Data() – Packet_Release_Time()

Slide 160

Slide 160 text

STL-FEC 기능 덕분에 STLTP 패킷 한 두개 깨져서는 송신기에 영향을 주지 않음. 45 Multiplexer Various UDP/IP Streams BBF, Timing, Control, etc. FEC Encoder Transmitter FEC Row RTP/UDP/IP Stream FEC Column RTP/UDP/IP Stream STL Receiver 8 SMPTE 2022-1 FEC Decoder 9 IP Content Tunnel SMPTE ST 2022-1 RTP/UDP/IP Stream FEC Row RTP/UDP/IP Stream FEC Column RTP/UDP/IP Stream 10 IP Tunnel RTP/UDP/IP Stream w/ Fixed Packet Size PLP Demultiplexer 11 Various UDP/IP Streams BBF, Timing, Control, etc. 12 13 Figure 8.1 STL Transmission diagram. The following paragraphs describe each of the call-outs, (1) through (13), in Figure 8.1. Items (1) through (5) are further detailed in the FEC Encoding Process Section 8.5.1 below. 1) The multiple paths represent the RTP/UDP/IP Streams that are generated for each PLP as described in Sections 8.2, 8.3, and 8.3.4. These are referred to as the Tunneled Packet Streams. 2) The PLP Mux is configured to accept packets from multiple RTP/UDP/IP multicast Streams to be tunneled. 3) The Tunneled Packets are grouped into fixed-size payloads to accommodate the SMPTE ST 2022-1 FEC process [8]. The STLTP RTP fields are defined to allow the Tunneled Packet Streams to be easily recovered and forwarded (refer to Section 8.6 below). The fixed packet size of the ST 2022-1 packets is not defined by this standard and is assumed to be configurable. It is expected that the packet size is within the typical 1500 MTU byte range limit. Note that the larger the packets the longer the latency when performing FEC Transmitter 1 Transmitter 2 Transmitter 3 ATSC A/324:2018 Scheduler / Studio to Transmitter Link 5 January 2018 payloads for easy reconstruction on the Data Consumer side. All other aspects of ST 2022-1 remain identical to the capabilities described in [8] including support for any FEC constraints detailed in Section 8 of that standard. Note that latency will be longer with larger packet lengths. 8.5 STL Transmission Protocol Design Figure 8.1 provides a detailed diagram of the portion of the broadcast Physical Layer chain described by this section. Refer to Figure 4.2 for a complete diagram of the system architecture. PLP Multiplexer Various UDP/IP Streams BBF, Timing, Control, etc. SMPTE 2022-1 FEC Encoder IP Tunnel RTP/UDP/IP Stream w/ Fixed Packet Size STL Transmitter IP Content Tunnel SM PTE ST 2022-1 RTP/UDP/IP Stream FEC Row RTP/UDP/IP Stream FEC Column RTP/UDP/IP Stream 1 2 3 4 5 6 7 STL STL Receiver 8 SM PTE 2022-1 FEC Decoder 9 IP Content Tunnel SMPTE ST 2022-1 RTP/UDP/IP Stream FEC Row RTP/UDP/IP Stream FEC Column RTP/UDP/IP Stream 10 IP Tunnel RTP/UDP/IP Stream w/ Fixed Packet Size PLP Demultiplexer 11 Various UDP/IP Streams BBF, Timing, Control, etc. 12 13 Figure 8.1 STL Transmission diagram. The following paragraphs describe each of the call-outs, (1) through (13), in Figure 8.1. Items (1) through (5) are further detailed in the FEC Encoding Process Section 8.5.1 below. 1) The multiple paths represent the RTP/UDP/IP Streams that are generated for each PLP as described in Sections 8.2, 8.3, and 8.3.4. These are referred to as the Tunneled Packet Streams. PLP Demux SMPTE ST 2022-1 ECC Decoder SMPTE ST 2022-1 ECC Encoder Authentication STL Rcvr STL Xmtr IP UDP RTP IP UDP RTP IP UDP RTP IP UDP RTP IP Packetizers Baseband Packetizers PLPs PLPs Scheduler Timing & Mgt Generator Preamble Generator ALP Demux ALP Mux IP UDP RTP ALPs ALP Encapsulation ALPs Data Source Data Source Data Source Data Source ALP Payload (ALPTP) STL Payload (STLTP) IP (ROUTE/MMT), TS, Generic Data In DSTP Payloads To System Manager (BXF) To/From Data Sources (MDCoIP) STL Link IP/UDP/RTP Microwave/Satellite/Fiber ≤ 1 Phy Frame Delay (≤ 5secs) ALP Buffers ALPs LLS Ind. Configuration Mgr STL Payload (STLTP) EAS Trig. Broadcast Gateway w/External ALP Gen Broadcast Gateway w/Internal ALP Gen IP UDP RTP PLP Mux PLPs USB Crypto Token Security Device Security Data Processor Security Data Stream PLPs Authentication USB Crypto Token Security Device Security Data Processor Keys Security Data Stream Keys Figure 4.2 System architecture. Figure 4.2 shows a possible system architecture; other configurations are possible. When nsidering system configurations, data rates and interfaces between functional blocks must be ken into account in developing practical implementations. System Manager onfiguration aspects of the overall system are controlled by a single entity called a System PLP De SMPTE ST 2022-1 ECC Decoder SMPTE ST 2022-1 ECC Encoder Authentication STL Rcvr STL Xmtr IP UDP RTP IP UDP RTP IP UDP RTP IP UDP RTP IP Packetizers Baseband Packetizers PLPs PLPs Scheduler Timing & Mgt Generator Preamble Generator ALP Demux ALP Mux IP UDP RTP ALPs ALP Encapsulation ALPs Data Source Data Source Data Source Data Source ALP Payload (ALPTP) STL Payload (STLTP) IP (ROUTE/MMT), TS, Generic Data In DSTP Payloads From/To System Manager (BXF) To/From Data Sources (MDCoIP) STL Link IP/UDP/RTP Microwave/Satellite/Fiber ≤ 1 Phy Frame Delay (≤ 5secs) ALP Buffers ALPs LLS Ind. Configuration Mgr STL Payload (STLTP) EAS Trig. Broadcast Gateway w/External ALP Gen Broadcast Gateway w/Internal ALP Gen IP UDP RTP PLP Mux PLPs USB Crypto Token Security Device Security Data Processor Security Data Stream Securit Keys Figure 4.2 System architecture. Figure 4.2 shows a possible system architecture; other configurations are possib considering system configurations, data rates and interfaces between functional block taken into account in developing practical implementations. System Manager Configuration aspects of the overall system are controlled by a single entity called PLP Demux SMPTE ST 2022-1 ECC Decoder SMPTE ST 2022-1 ECC Encoder Authentication STL Rcvr STL Xmtr IP UDP RTP IP UDP RTP IP UDP RTP IP UDP RTP IP Packetizers Baseband Packetizers PLPs PLPs Scheduler Timing & Mgt Generator Preamble Generator ALP Demux ALP Mux IP UDP RTP ALPs ALP Encapsulation ALPs Data Source Data Source Data Source Data Source ALP Payload (ALPTP) STL Payload (STLTP) IP (ROUTE/MMT), TS, Generic Data In DSTP Payloads o System Manager (BXF) To/From Data Sources (MDCoIP) STL Link IP/UDP/RTP Microwave/Satellite/Fiber ≤ 1 Phy Frame Delay (≤ 5secs) ALP Buffers ALPs LLS Ind. Configuration Mgr STL Payload (STLTP) EAS Trig. Broadcast Gateway w/External ALP Gen Broadcast Gateway w/Internal ALP Gen IP UDP RTP PLP Mux PLPs USB Crypto Token Security Device Security Data Processor Security Data Stream PLPs Authentication USB Crypto Token Security Device Security Data Processor Keys Security Data Stream Keys Figure 4.2 System architecture. Figure 4.2 shows a possible system architecture; other configurations are possible. Whe nsidering system configurations, data rates and interfaces between functional blocks must b ken into account in developing practical implementations. System Manager onfiguration aspects of the overall system are controlled by a single entity called a System PLP Demux SMPTE ST 2022-1 ECC Decoder SMPTE ST 2022-1 ECC Encoder Authentication STL Rcvr STL Xmtr IP UDP RTP IP UDP RTP IP UDP RTP IP UDP RTP IP Packetizers Baseband Packetizers PLPs PLPs Scheduler Timing & Mgt Generator Preamble Generator ALP Demux ALP Mux IP UDP RTP ALPs ALP Encapsulation ALPs Data Source Data Source Data Source Data Source ALP Payload (ALPTP) STL Payload (STLTP) IP (ROUTE/MMT), TS, Generic Data In DSTP Payloads o System Manager (BXF) To/From Data Sources (MDCoIP) STL Link IP/UDP/RTP Microwave/Satellite/Fiber ≤ 1 Phy Frame Delay (≤ 5secs) ALP Buffers ALPs LLS Ind. Configuration Mgr STL Payload (STLTP) EAS Trig. Broadcast Gateway w/External ALP Gen Broadcast Gateway w/Internal ALP Gen IP UDP RTP PLP Mux PLPs USB Crypto Token Security Device Security Data Processor Security Data Stream PLPs Authentication USB Crypto Token Security Device Security Data Processor Keys Security Data Stream Keys Figure 4.2 System architecture. Figure 4.2 shows a possible system architecture; other configurations are possible. Whe nsidering system configurations, data rates and interfaces between functional blocks must b ken into account in developing practical implementations. System Manager onfiguration aspects of the overall system are controlled by a single entity called a System PLP Demux SMPTE ST 2022-1 ECC Decoder SMPTE ST 2022-1 ECC Encoder Authentication STL Rcvr STL Xmtr IP UDP RTP IP UDP RTP IP UDP RTP IP UDP RTP IP Packetizers Baseband Packetizers PLPs PLPs Scheduler Timing & Mgt Generator Preamble Generator ALP Demux ALP Mux IP UDP RTP ALPs ALP Encapsulation ALPs Data Source Data Source Data Source Data Source ALP Payload (ALPTP) STL Payload (STLTP) IP (ROUTE/MMT), TS, Generic Data In DSTP Payloads o System Manager (BXF) To/From Data Sources (MDCoIP) STL Link IP/UDP/RTP Microwave/Satellite/Fiber ≤ 1 Phy Frame Delay (≤ 5secs) ALP Buffers ALPs LLS Ind. Configuration Mgr STL Payload (STLTP) EAS Trig. Broadcast Gateway w/External ALP Gen Broadcast Gateway w/Internal ALP Gen IP UDP RTP PLP Mux PLPs USB Crypto Token Security Device Security Data Processor Security Data Stream PLPs Authentication USB Crypto Token Security Device Security Data Processor Keys Security Data Stream Keys Figure 4.2 System architecture. Figure 4.2 shows a possible system architecture; other configurations are possible. Whe nsidering system configurations, data rates and interfaces between functional blocks must b ken into account in developing practical implementations. System Manager onfiguration aspects of the overall system are controlled by a single entity called a System PLP Demux SMPTE ST 2022-1 ECC Decoder SMPTE ST 2022-1 ECC Encoder Authentication STL Rcvr STL Xmtr IP UDP RTP IP UDP RTP IP UDP RTP IP UDP RTP IP Packetizers Baseband Packetizers PLPs PLPs Scheduler Timing & Mgt Generator Preamble Generator ALP Demux ALP Mux IP UDP RTP ALPs ALP Encapsulation ALPs Data Source Data Source Data Source Data Source ALP Payload (ALPTP) STL Payload (STLTP) IP (ROUTE/MMT), TS, Generic Data In DSTP Payloads o System Manager (BXF) To/From Data Sources (MDCoIP) STL Link IP/UDP/RTP Microwave/Satellite/Fiber ≤ 1 Phy Frame Delay (≤ 5secs) ALP Buffers ALPs LLS Ind. Configuration Mgr STL Payload (STLTP) EAS Trig. Broadcast Gateway w/External ALP Gen Broadcast Gateway w/Internal ALP Gen IP UDP RTP PLP Mux PLPs USB Crypto Token Security Device Security Data Processor Security Data Stream PLPs Authentication USB Crypto Token Security Device Security Data Processor Keys Security Data Stream Keys Figure 4.2 System architecture. Figure 4.2 shows a possible system architecture; other configurations are possible. Whe nsidering system configurations, data rates and interfaces between functional blocks must b ken into account in developing practical implementations. System Manager PLP Demux SMPTE ST 2022-1 ECC Decoder SMPTE ST 2022-1 ECC Encoder Authentication STL Rcvr STL Xmtr IP UDP RTP IP UDP RTP IP UDP RTP IP UDP RTP IP Packetizers Baseband Packetizers PLPs PLPs Scheduler Timing & Mgt Generator Preamble Generator ALP Demux ALP Mux IP UDP RTP ALPs ALP Encapsulation ALPs Data Source Data Source Data Source Data Source ALP Payload (ALPTP) STL Payload (STLTP) IP (ROUTE/MMT), TS, Generic Data In DSTP Payloads (BXF) To/From Data Sources (MDCoIP) STL Link IP/UDP/RTP Microwave/Satellite/Fiber ≤ 1 Phy Frame Delay (≤ 5secs) ALP Buffers ALPs LLS Ind. STL Payload (STLTP) EAS Trig. w/External ALP Gen w/Internal ALP Gen IP UDP RTP PLP Mux PLPs USB Crypto Token Security Device Security Data Processor Security Data Stream PLPs Authentication USB Crypto Token Security Device Security Data Processor Keys Security Data Stream Keys Figure 4.2 System architecture. Figure 4.2 shows a possible system architecture; other configurations are possible. Wh nsidering system configurations, data rates and interfaces between functional blocks must ken into account in developing practical implementations. System Manager nfiguration aspects of the overall system are controlled by a single entity called a Syste anager, which is represented in Figure 4.2 only as a connection to the Configuration Manager PLP Demux SMPTE ST 2022-1 ECC Decoder SMPTE ST 2022-1 ECC Encoder hentication STL Rcvr STL Xmtr IP UDP RTP IP UDP RTP IP UDP RTP IP UDP RTP Timing & Mgt Generator STL Payload (STLTP) STL Link IP/UDP/RTP Microwave/Satellite/Fiber STL Payload (STLTP) ALP Gen PLP Mux PLPs USB Crypto Token Security Device Security Data Processor Security Data Stream PLPs Authentication USB Crypto Token Security Device Security Data Processor Keys Security Data Stream Keys ystem architecture. hitecture; other configurations are possible. When and interfaces between functional blocks must be plementations. are controlled by a single entity called a System nly as a connection to the Configuration Manager in an be anything from a web-page based setup screen Korean Broadcasting System | Broadcast Technical Research Institute Bit Int’l FEC Mapper LDM MIMO Time Int’l OFDM Framer/ Preamble Inserter Freq Int’l Pilot/ Tone Reserve MISO IFFT PAPR GI Bootst Spectr Shap ≤ 1sec Network Comp. Buffers PLPs PLPs PLPs PLPs PLPs PLPs PLPs PHY Fr PHY Fr PHY Fr PHY Fr PHY Fr PHY Fr PHY Fr PLP Demux SMPTE ST 2022-1 ECC Decoder SMPTE ST 2022-1 ECC Encoder Authentication STL Rcvr STL Xmtr IP UDP RTP IP UDP RTP IP UDP RTP IP UDP RTP IP Packetizers Baseband Packetizers PLPs PLPs Scheduler Timing & Mgt Generator Preamble Generator ALP Demux ALP Mux IP UDP RTP ALPs ALP Encapsulation ALPs Data Source Data Source Data Source Data Source Scrambler PLPs ALP Payload (ALPTP) STL Payload (STLTP) IP (ROUTE/MMT), TS, Generic Data In DSTP Payloads From/To System Manager (BXF) To/From Data Sources (MDCoIP) STL Link IP/UDP/RTP Microwave/Satellite/Fiber ≤ 1 Phy Frame Delay (≤ 5secs) ALP Buffers ALPs LLS Ind. Configuration Mgr STL Payload (STLTP) EAS Trig. Broadcast Gateway w/External ALP Gen Broadcast Gateway w/Internal ALP Gen IP UDP RTP PLP Mux PLPs USB Crypto Token Security Device Security Data Processor Security Data Stream PL Securi Da Process Security Data S Keys Figure 4.2 System architecture. Figure 4.2 shows a possible system architecture; other configurations are possible Bit Int’l FEC Mapper LDM MIMO Time Int’l OFDM Framer/ Preamble Inserter Freq Int’l Pilot/ Tone Reserve MISO IFFT PAPR ≤ 1sec Network Comp. Buffers Preamble Parser PLPs PLPs PLPs PLPs PLPs PLPs PLPs PHY Fr PHY Fr PHY Fr PHY Fr PHY Fr SMPTE ST 2022-1 ECC Encoder Authentication STL Rcvr STL Xmtr IP UDP RTP IP UDP RTP IP UD RT IP Packetizers Baseband Packetizers PLPs PLPs Scheduler Timing & Mgt Generator Preamble Generator ALP Demux ALP Mux IP UDP RTP ALPs ALP Encapsulation ALPs Data Source Data Source Data Source Data Source Scrambler PLPs ALP Payload (ALPTP) STL Payload (STLTP) IP (ROUTE/MMT), TS, Generic Data In DSTP Payloads From/To System Manager (BXF) To/From Data Sources (MDCoIP) STL Link IP/UDP/RTP Microwave/Satellite/Fiber ≤ 1 Phy Frame Delay (≤ 5secs) ALP Buffers ALPs LLS Ind. Configuration Mgr EAS Trig. Broadcast Gateway w/External ALP Gen Broadcast Gateway w/Internal ALP Gen IP UDP RTP PLP Mux PLPs USB Crypto Token Security Device Security Data Processor Security Data Stream Keys Figure 4.2 System architecture. Figure 4.2 shows a possible system architecture; other configurations ar Bit Int’l FEC Mapper LDM MIMO Time Int’l OFDM Framer/ Preamble Inserter Freq Int’l Pilot/ Tone Reserve MISO IFFT PAPR GI Boots Spec Sha ≤ 1sec Network Comp. Buffers Preamble Parser PLPs PLPs PLPs PLPs PLPs PLPs PLPs PHY Fr PHY Fr PHY Fr PHY Fr PHY Fr PHY Fr PHY Fr PLP Demux SMPTE ST 2022-1 ECC Decoder SMPTE ST 2022-1 ECC Encoder Authentication STL Rcvr STL Xmtr IP UDP RTP IP UDP RTP IP UDP RTP IP UDP RTP IP Packetizers Baseband Packetizers PLPs PLPs Scheduler Timing & Mgt Generator Preamble Generator ALP Demux ALP Mux IP UDP RTP ALPs ALP Encapsulation ALPs Data Source Data Source Data Source Data Source Scrambler PLPs ALP Payload (ALPTP) STL Payload (STLTP) IP (ROUTE/MMT), TS, Generic Data In DSTP Payloads From/To System Manager (BXF) To/From Data Sources (MDCoIP) STL Link IP/UDP/RTP Microwave/Satellite/Fiber ≤ 1 Phy Frame Delay (≤ 5secs) ALP Buffers ALPs LLS Ind. Configuration Mgr STL Payload (STLTP) EAS Trig. Broadcast Gateway w/External ALP Gen Broadcast Gateway w/Internal ALP Gen IP UDP RTP PLP Mux PLPs USB Crypto Token Security Device Security Data Processor Security Data Stream P Secu D Proces Security Data Keys Figure 4.2 System architecture. Bit Int’l FEC Mapper LDM MIMO Time Int’l OFDM Framer/ Preamble Inserter Freq Int’l Pilot/ Tone Reserve MISO IFFT PAPR GI Boots Spec Sha ≤ 1sec Network Comp. Buffers PLPs PLPs PLPs PLPs PLPs PLPs PLPs PHY Fr PHY Fr PHY Fr PHY Fr PHY Fr PHY Fr PHY Fr PLP Demux SMPTE ST 2022-1 ECC Decoder SMPTE ST 2022-1 ECC Encoder Authentication STL Rcvr STL Xmtr IP UDP RTP IP UDP RTP IP UDP RTP IP UDP RTP IP Packetizers Baseband Packetizers PLPs PLPs Scheduler Timing & Mgt Generator Preamble Generator ALP Demux ALP Mux IP UDP RTP ALPs ALP Encapsulation ALPs Data Source Data Source Data Source Data Source Scrambler PLPs ALP Payload (ALPTP) STL Payload (STLTP) IP (ROUTE/MMT), TS, Generic Data In DSTP Payloads From/To System Manager (BXF) To/From Data Sources (MDCoIP) STL Link IP/UDP/RTP Microwave/Satellite/Fiber ≤ 1 Phy Frame Delay (≤ 5secs) ALP Buffers ALPs LLS Ind. Configuration Mgr STL Payload (STLTP) EAS Trig. Broadcast Gateway w/External ALP Gen Broadcast Gateway w/Internal ALP Gen IP UDP RTP PLP Mux PLPs USB Crypto Token Security Device Security Data Processor Security Data Stream P Secu D Proces Security Data Keys Figure 4.2 System architecture. Figure 4.2 shows a possible system architecture; other configurations are possible Bit Int’l FEC Mapper LDM MIMO Time Int’l OFDM Framer/ Preamble Inserter Freq Int’l Pilot/ Tone Reserve MISO IFFT PAPR GI Boots Spec Sha ≤ 1sec Network Comp. Buffers PLPs PLPs PLPs PLPs PLPs PLPs PLPs PHY Fr PHY Fr PHY Fr PHY Fr PHY Fr PHY Fr PHY Fr PLP Demux SMPTE ST 2022-1 ECC Decoder SMPTE ST 2022-1 ECC Encoder Authentication STL Rcvr STL Xmtr IP UDP RTP IP UDP RTP IP UDP RTP IP UDP RTP IP Packetizers Baseband Packetizers PLPs PLPs Scheduler Timing & Mgt Generator Preamble Generator ALP Demux ALP Mux IP UDP RTP ALPs ALP Encapsulation ALPs Data Source Data Source Data Source Data Source Scrambler PLPs ALP Payload (ALPTP) STL Payload (STLTP) IP (ROUTE/MMT), TS, Generic Data In DSTP Payloads From/To System Manager (BXF) To/From Data Sources (MDCoIP) STL Link IP/UDP/RTP Microwave/Satellite/Fiber ≤ 1 Phy Frame Delay (≤ 5secs) ALP Buffers ALPs LLS Ind. Configuration Mgr STL Payload (STLTP) EAS Trig. Broadcast Gateway w/External ALP Gen Broadcast Gateway w/Internal ALP Gen IP UDP RTP PLP Mux PLPs USB Crypto Token Security Device Security Data Processor Security Data Stream P Secu D Proces Security Data Keys Figure 4.2 System architecture. Figure 4.2 shows a possible system architecture; other configurations are possible Korean Broadcasting System | Broadcast Technical Research Institute Bit Int’l FEC Mapper LDM MIMO Time Int’l OFDM Framer/ Preamble Inserter Freq Int’l Pilot/ Tone Reserve MISO IFFT PAPR GI B S ≤ 1sec Network Comp. Buffers PLPs PLPs PLPs PLPs PLPs PLPs PLPs PHY Fr PHY Fr PHY Fr PHY Fr PHY Fr PHY Fr PHY Fr PLP Demu SMPTE ST 2022-1 ECC Decoder SMPTE ST 2022-1 ECC Encoder Authentication STL Rcvr STL Xmtr IP UDP RTP IP UDP RTP IP UDP RTP IP UDP RTP IP Packetizers Baseband Packetizers PLPs PLPs Scheduler Timing & Mgt Generator Preamble Generator ALP Demux ALP Mux IP UDP RTP ALPs ALP Encapsulation ALPs Data Source Data Source Data Source Data Source Scrambler PLPs ALP Payload (ALPTP) STL Payload (STLTP) IP (ROUTE/MMT), TS, Generic Data In DSTP Payloads From/To System Manager (BXF) To/From Data Sources (MDCoIP) STL Link IP/UDP/RTP Microwave/Satellite/Fiber ≤ 1 Phy Frame Delay (≤ 5secs) ALP Buffers ALPs LLS Ind. Configuration Mgr STL Payload (STLTP) EAS Trig. Broadcast Gateway w/External ALP Gen Broadcast Gateway w/Internal ALP Gen IP UDP RTP PLP Mux PLPs USB Crypto Token Security Device Security Data Processor Security Data Stream S Pr Security D Keys Figure 4.2 System architecture. Figure 4.2 shows a possible system architecture; other configurations are possib Bit Int’l FEC Mapper LDM MIMO Time Int’l OFDM Framer/ Preamble Inserter Freq Int’l Pilot/ Tone Reserve MISO IFFT ≤ 1sec Network Comp. Buffers Preamble Parser PLPs PLPs PLPs PLPs PLPs PLPs PLPs PHY Fr PHY Fr PHY Fr PHY Fr PHY Fr SMPTE ST 2022-1 ECC Encoder Authentication STL Rcvr STL Xmtr IP UDP RTP IP UDP RTP IP Packetizers Baseband Packetizers PLPs PLPs Scheduler Timing & Mgt Generator Preamble Generator ALP Demux ALP Mux IP UDP RTP ALPs ALP Encapsulation ALPs Data Source Data Source Data Source Data Source Scrambler PLPs ALP Payload (ALPTP) STL Payload (STLTP) IP (ROUTE/MMT), TS, Generic Data In DSTP Payloads From/To System Manager (BXF) To/From Data Sources (MDCoIP) STL Link IP/UDP/RTP Microwave/Satellite/Fiber ≤ 1 Phy Frame Delay (≤ 5secs) ALP Buffers ALPs LLS Ind. Configuration Mgr EAS Trig. Broadcast Gateway w/External ALP Gen Broadcast Gateway w/Internal ALP Gen IP UDP RTP PLP Mux PLPs USB Crypto Token Security Device Security Data Processor Security Data Stream Keys Figure 4.2 System architecture. Figure 4.2 shows a possible system architecture; other configurations Bit Int’l FEC Mapper LDM MIMO Time Int’l OFDM Framer/ Preamble Inserter Freq Int’l Pilot/ Tone Reserve MISO IFFT PAPR GI ≤ 1sec Network Comp. Buffers Preamble Parser PLPs PLPs PLPs PLPs PLPs PLPs PLPs PHY Fr PHY Fr PHY Fr PHY Fr PHY Fr PHY Fr PHY Fr PLP Dem SMPTE ST 2022-1 ECC Decoder SMPTE ST 2022-1 ECC Encoder Authentication STL Rcvr STL Xmtr IP UDP RTP IP UDP RTP IP UDP RTP IP UDP RTP IP Packetizers Baseband Packetizers PLPs PLPs Scheduler Timing & Mgt Generator Preamble Generator ALP Demux ALP Mux IP UDP RTP ALPs ALP Encapsulation ALPs Data Source Data Source Data Source Data Source Scrambler PLPs ALP Payload (ALPTP) STL Payload (STLTP) IP (ROUTE/MMT), TS, Generic Data In DSTP Payloads From/To System Manager (BXF) To/From Data Sources (MDCoIP) STL Link IP/UDP/RTP Microwave/Satellite/Fiber ≤ 1 Phy Frame Delay (≤ 5secs) ALP Buffers ALPs LLS Ind. Configuration Mgr STL Payload (STLTP) EAS Trig. Broadcast Gateway w/External ALP Gen Broadcast Gateway w/Internal ALP Gen IP UDP RTP PLP Mux PLPs USB Crypto Token Security Device Security Data Processor Security Data Stream P Security Keys Figure 4.2 System architecture. Bit Int’l FEC Mapper LDM MIMO Time Int’l OFDM Framer/ Preamble Inserter Freq Int’l Pilot/ Tone Reserve MISO IFFT PAPR GI ≤ 1sec Network Comp. Buffers PLPs PLPs PLPs PLPs PLPs PLPs PLPs PHY Fr PHY Fr PHY Fr PHY Fr PHY Fr PHY Fr PHY Fr PLP Dem SMPTE ST 2022-1 ECC Decoder SMPTE ST 2022-1 ECC Encoder Authentication STL Rcvr STL Xmtr IP UDP RTP IP UDP RTP IP UDP RTP IP UDP RTP IP Packetizers Baseband Packetizers PLPs PLPs Scheduler Timing & Mgt Generator Preamble Generator ALP Demux ALP Mux IP UDP RTP ALPs ALP Encapsulation ALPs Data Source Data Source Data Source Data Source Scrambler PLPs ALP Payload (ALPTP) STL Payload (STLTP) IP (ROUTE/MMT), TS, Generic Data In DSTP Payloads From/To System Manager (BXF) To/From Data Sources (MDCoIP) STL Link IP/UDP/RTP Microwave/Satellite/Fiber ≤ 1 Phy Frame Delay (≤ 5secs) ALP Buffers ALPs LLS Ind. Configuration Mgr STL Payload (STLTP) EAS Trig. Broadcast Gateway w/External ALP Gen Broadcast Gateway w/Internal ALP Gen IP UDP RTP PLP Mux PLPs USB Crypto Token Security Device Security Data Processor Security Data Stream P Security Keys Figure 4.2 System architecture. Figure 4.2 shows a possible system architecture; other configurations are possib Bit Int’l FEC Mapper LDM MIMO Time Int’l OFDM Framer/ Preamble Inserter Freq Int’l Pilot/ Tone Reserve MISO IFFT PAPR GI ≤ 1sec Network Comp. Buffers PLPs PLPs PLPs PLPs PLPs PLPs PLPs PHY Fr PHY Fr PHY Fr PHY Fr PHY Fr PHY Fr PHY Fr PLP Dem SMPTE ST 2022-1 ECC Decoder SMPTE ST 2022-1 ECC Encoder Authentication STL Rcvr STL Xmtr IP UDP RTP IP UDP RTP IP UDP RTP IP UDP RTP IP Packetizers Baseband Packetizers PLPs PLPs Scheduler Timing & Mgt Generator Preamble Generator ALP Demux ALP Mux IP UDP RTP ALPs ALP Encapsulation ALPs Data Source Data Source Data Source Data Source Scrambler PLPs ALP Payload (ALPTP) STL Payload (STLTP) IP (ROUTE/MMT), TS, Generic Data In DSTP Payloads From/To System Manager (BXF) To/From Data Sources (MDCoIP) STL Link IP/UDP/RTP Microwave/Satellite/Fiber ≤ 1 Phy Frame Delay (≤ 5secs) ALP Buffers ALPs LLS Ind. Configuration Mgr STL Payload (STLTP) EAS Trig. Broadcast Gateway w/External ALP Gen Broadcast Gateway w/Internal ALP Gen IP UDP RTP PLP Mux PLPs USB Crypto Token Security Device Security Data Processor Security Data Stream P Security Keys Figure 4.2 System architecture. Figure 4.2 shows a possible system architecture; other configurations are possib SM ST 20 EC Dec SMPTE ST 2022-1 ECC Encoder Authentication STL Rcvr STL Xmtr IP UDP RTP IP UDP RTP IP UDP RTP IP Packetizers Baseband Packetizers PLPs PLPs Scheduler & Mgt Generator Preamble Generator ALP Demux ALP Mux IP UDP RTP ALPs ALP Encapsulation ALPs Data Source Data Source Data Source Data Source ALP Payload (ALPTP) STL Payload (STLTP) IP (ROUTE/MMT), TS, Generic Data In DSTP Payloads STL Link IP/UDP/RTP Microwave/Satellite/Fiber ≤ 1 Phy Frame Delay (≤ 5secs) ALP Buffers ALPs LLS Ind. EAS Trig. IP UDP RTP PLP Mux PLPs Device Data Processor Security Data Stream Keys Figure 4.2 System architecture. Figure 4.2 shows a possible system architecture; other configurations are considering system configurations, data rates and interfaces between functional taken into account in developing practical implementations. System Manager Configuration aspects of the overall system are controlled by a single entity c Manager, which is represented in Figure 4.2 only as a connection to the Configura the Broadcast Gateway. A System Manager can be anything from a web-page bas with manual data entry to a fully automated system; its scope is control of an ov system. The System Manager provides high-level configuration parameters for nu Bit Int’l FEC Mapper LDM MIMO Time Int’l OFDM Framer/ Preamble Inserter Freq Int’l Pilot/ Tone Reserve MISO IFFT PAPR ≤ 1sec Network Comp. Buffers Fr Fr Fr Fr Fr ST D SMPTE ST 2022-1 ECC Encoder Authentication STL Rcvr STL Xmtr IP UDP RTP IP UDP RTP IP UDP RTP IP Packetizers Baseband Packetizers PLPs PLPs Scheduler Timing & Mgt Generator Preamble Generator ALP Demux ALP Mux IP UDP RTP ALPs ALP Encapsulation ALPs Data Source Data Source Data Source Data Source Scrambler PLPs ALP Payload (ALPTP) STL Payload (STLTP) IP (ROUTE/MMT), TS, Generic Data In DSTP Payloads From/To System Manager (BXF) To/From Data Sources (MDCoIP) STL Link IP/UDP/RTP Microwave/Satellite/Fiber ≤ 1 Phy Frame Delay (≤ 5secs) ALP Buffers ALPs LLS Ind. Configuration Mgr EAS Trig. Broadcast Gateway w/External ALP Gen Broadcast Gateway w/Internal ALP Gen IP UDP RTP PLP Mux PLPs USB Crypto Token Security Device Security Data Processor Security Data Stream Keys Figure 4.2 System architecture. ATSC S32-266r33 Revision of A/324:2018, S Bit Int’l FEC Mapper LDM MIMO ≤ 1sec Network Comp. Buffers Preamble Parser PLPs PLPs PLPs PLPs Timing Manager B U F F E R B U F F E R PLPs GNSS Time TAD IP Packetizer Baseband Packetizers PLPs Scheduler Preamble Generator ALP Demux ALP Mux IP UDP RTP ALPs ALP Encapsulation ALPs Data Source Data Source Data Source Data Source Scrambler PLPs ALP Payload (ALPTP) IP (ROUTE/MMT), TS, Generic Data In DSTP Payloads From/To System Manager (BXF) To/From Data Sources (MDCoIP) ≤ 1 Phy Frame Delay (≤ 5secs) ALP Buffers ALPs LLS Ind. Configuration Mgr EAS Trig. Broadcast Gateway w/Internal ALP Gen IP UDP RTP Figure 4.2 ALP Mux ALP Encapsulation ALPs Data Source Data Source Data Source Data Source IP (ROUTE/MMT), TS, Generic Data In DSTP Payloads From/To System Manager (BXF) To/From Data Sources (MDCoIP) Broadcast Gateway w/Internal ALP Gen IP UDP RTP Figure 4.2 sho considering system taken into account i System Man Configuration aspe Manager, which is r the Broadcast Gate with manual data e system. The System functions. The Syst chain. It controls th configurations of t sessions that suppo SMPTE ST 2022-1 ECC Encoder Authentication STL Xmtr IP UDP RTP IP UDP RTP IP Packetizers Baseband Packetizers PLPs PLPs Scheduler Timing & Mgt Generator Preamble Generator ALP Demux ALP Mux IP UDP RTP ALPs ALP Encapsulation ALPs Data Source Data Source Data Source Data Source ALP Payload (ALPTP) STL Payload (STLTP) IP (ROUTE/MMT), TS, Generic Data In DSTP Payloads Data Sources (MDCoIP) STL Lin IP/UDP/R Microwave/Sate ≤ 1 Phy Frame Delay (≤ 5secs) ALP Buffers ALPs LLS Ind. EAS Trig. IP UDP RTP PLP Mux PLPs Token Security Device Security Data Processor Security Data Stream Keys Figure 4.2 System architecture. Figure 4.2 shows a possible system architecture; other configur considering system configurations, data rates and interfaces between taken into account in developing practical implementations. System Manager Configuration aspects of the overall system are controlled by a sing SMPTE ST 2022-1 ECC Encoder Authentication STL Xmtr IP UDP RTP IP UDP RTP IP Packetizers Baseband Packetizers PLPs PLPs Scheduler Timing & Mgt Generator Preamble Generator ALP Demux ALP Mux IP UDP RTP ALPs ALP Encapsulation ALPs Data Source Data Source Data Source Data Source ALP Payload (ALPTP) STL Payload (STLTP) IP (ROUTE/MMT), TS, Generic Data In DSTP Payloads Data Sources (MDCoIP) STL Link IP/UDP/RTP Microwave/Satellite/Fiber ≤ 1 Phy Frame Delay (≤ 5secs) ALP Buffers ALPs LLS Ind. EAS Trig. IP UDP RTP PLP Mux PLPs Token Security Device Security Data Processor Security Data Stream Keys Figure 4.2 System architecture. Figure 4.2 shows a possible system architecture; other configuratio considering system configurations, data rates and interfaces between fun taken into account in developing practical implementations. System Manager Configuration aspects of the overall system are controlled by a single ECC Decoding & STLTP Demultiplexing STL Rcvr STL Xmtr IP UDP RTP IP UDP RTP STLTP Formatting & ECC Encoding STL Pre-Processor PLPs Configuration Mgr /Scheduler ALPTP Receiver ALPTP Formatting IP UDP RTP ALPs ALPTP STLTP STL Link IP/UDP/RTP Microwave/Satellite/Fiber Preamble Information Timing & Mgt Information STLTP Coded Modulation Input Formatting Framing/ Structure Waveform Generation Preamble Parser Buffer Broadcast Gateway Figure 4.1 High-level overview of system configuration. o-one correspondence between individual Streams of ALP packets and prepare ALP packets for Transmission, in the Broadcast Gateway, the ALP lated in Baseband Packets (BBPs), which have defined sizes that are meter (Kpayload) related to the specific characteristics of the particular PLP(s) e carried. The sizes of the BBPs in a given Stream are set to assure that the the related PLP in a frame is filled by the BBPs derived from an associated ALP packets either are segmented or are concatenated so that they fill the e BBPs carrying them as completely as possible without overflowing the ow of data through the system, several buffers are required to hold data for ECC Decoding & STLTP Demultiplexing STL Rcvr STL Xmtr IP UDP RTP IP UDP RTP STLTP Formatting & ECC Encoding STL Pre-Processor PLPs Configuration Mgr /Scheduler ALPTP Receiver ALPTP Formatting IP UDP RTP ALPs ALP Generation ALPs Data Sources ALPTP STLTP STL Link IP/UDP/RTP Microwave/Satellite/Fiber ATSC A/330 ALP & A/331 Signaling, etc. Transport Layer System Manager Preamble Information Timing & Mgt Information STLTP Coded Modulation Input Formatting Framing/ Structure Waveform Generation Preamble Parser Buffer Broadcast Gateway DSTP Broadcast Gateway w/Internal ALP Gen. Figure 4.1 High-level overview of system configuration. There is a one-to-one correspondence between individual Streams of ALP packets and individual PLPs. To prepare ALP packets for Transmission, in the Broadcast Gateway, the ALP packets are encapsulated in Baseband Packets (BBPs), which have defined sizes that are determined by a parameter (Kpayload) related to the specific characteristics of the particular PLP(s) in which they will be carried. The sizes of the BBPs in a given Stream are set to assure that the assigned capacity of the related PLP in a frame is filled by the BBPs derived from an associated ALP packet Stream. ALP packets either are segmented or are concatenated so that they fill the allocated space in the BBPs carrying them as completely as possible without overflowing the available space. ECC Decoding & STLTP Demultiplexing STL Rcvr STL Xmtr IP UDP RTP IP UDP RTP STLTP Formatting & ECC Encoding STL Pre-Processor PLPs Configuration Mgr /Scheduler ALPTP Receiver ALPTP Formatting IP UDP RTP ALPs ALP Generation ALPs Data Sources ALPTP STLTP STL Link IP/UDP/RTP Microwave/Satellite/Fiber ATSC A/330 ALP & A/331 Signaling, etc. Transport Layer System Manager Preamble Information Timing & Mgt Information STLTP Coded Modulation Input Formatting Framing/ Structure Waveform Generation Parser Buffer Broadcast Gateway DSTP Broadcast Gateway w/Internal ALP Gen. Figure 4.1 High-level overview of system configuration. There is a one-to-one correspondence between individual Streams of ALP packets and individual PLPs. To prepare ALP packets for Transmission, in the Broadcast Gateway, the ALP packets are encapsulated in Baseband Packets (BBPs), which have defined sizes that are determined by a parameter (Kpayload) related to the specific characteristics of the particular PLP(s) in which they will be carried. The sizes of the BBPs in a given Stream are set to assure that the assigned capacity of the related PLP in a frame is filled by the BBPs derived from an associated ALP packet Stream. ALP packets either are segmented or are concatenated so that they fill the allocated space in the BBPs carrying them as completely as possible without overflowing the available space. ECC Decoding & STLTP Demultiplexing STL Rcvr STL Xmtr IP UDP RTP IP UDP RTP STLTP Formatting & ECC Encoding STL Pre-Processor PLPs Configuration Mgr /Scheduler ALPTP Receiver ALPTP Formatting IP UDP RTP ALPs s ALPTP STLTP STL Link IP/UDP/RTP Microwave/Satellite/Fiber Preamble Information Timing & Mgt Information STLTP Broadcast Gateway t al Figure 4.1 High-level overview of system configuration. -to-one correspondence between individual Streams of ALP packets and prepare ALP packets for Transmission, in the Broadcast Gateway, the ALP ulated in Baseband Packets (BBPs), which have defined sizes that are ameter (Kpayload) related to the specific characteristics of the particular PLP(s) be carried. The sizes of the BBPs in a given Stream are set to assure that the f the related PLP in a frame is filled by the BBPs derived from an associated . ALP packets either are segmented or are concatenated so that they fill the he BBPs carrying them as completely as possible without overflowing the flow of data through the system, several buffers are required to hold data for ignment of data emission. Buffering also is required in certain instances to o be obtained from a data Stream and used to control particular functionality e the corresponding data is processed further. Two specific instances of such e system. The first buffer inserts at least one Physical Layer frame of delay in ECC Decoding & STLTP Demultiplexing STL Rcvr STL Xmtr IP UDP RTP IP UDP RTP STLTP Formatting & ECC Encoding STL Pre-Processor PLPs Configuration Mgr /Scheduler ALPTP Receiver TP tting IP UDP RTP ALPs ALPTP STLTP STL Link IP/UDP/RTP Microwave/Satellite/Fiber Preamble Information Timing & Mgt Information STLTP Broadcast Gateway ure 4.1 High-level overview of system configuration. one correspondence between individual Streams of ALP packets and epare ALP packets for Transmission, in the Broadcast Gateway, the ALP ed in Baseband Packets (BBPs), which have defined sizes that are ter (Kpayload) related to the specific characteristics of the particular PLP(s) arried. The sizes of the BBPs in a given Stream are set to assure that the e related PLP in a frame is filled by the BBPs derived from an associated LP packets either are segmented or are concatenated so that they fill the BBPs carrying them as completely as possible without overflowing the of data through the system, several buffers are required to hold data for ment of data emission. Buffering also is required in certain instances to e obtained from a data Stream and used to control particular functionality e corresponding data is processed further. Two specific instances of such ECC Decoding & STLTP Demultiplexing STL Rcvr STL Xmtr IP UDP RTP IP UDP RTP STLTP Formatting & ECC Encoding STL Pre-Processor PLPs Configuration Mgr /Scheduler ALPTP Receiver ALPTP Formatting IP UDP RTP ALPs ALPTP STLTP STL Link IP/UDP/RTP Microwave/Satellite/Fiber Preamble Information Timing & Mgt Information STLTP Broadcast Gateway t l Figure 4.1 High-level overview of system configuration. -to-one correspondence between individual Streams of ALP packets and prepare ALP packets for Transmission, in the Broadcast Gateway, the ALP ulated in Baseband Packets (BBPs), which have defined sizes that are ameter (Kpayload) related to the specific characteristics of the particular PLP(s) e carried. The sizes of the BBPs in a given Stream are set to assure that the the related PLP in a frame is filled by the BBPs derived from an associated ALP packets either are segmented or are concatenated so that they fill the he BBPs carrying them as completely as possible without overflowing the low of data through the system, several buffers are required to hold data for ignment of data emission. Buffering also is required in certain instances to o be obtained from a data Stream and used to control particular functionality e the corresponding data is processed further. Two specific instances of such e system. The first buffer inserts at least one Physical Layer frame of delay in sor to enable sending Preamble information for a given Physical Layer frame ECC Decoding & STLTP Demultiplexing STL Rcvr STL Xmtr IP UDP RTP IP UDP RTP STLTP Formatting & ECC Encoding STL Pre-Processor PLPs Configuration Mgr /Scheduler ALPTP Receiver TP tting IP UDP RTP ALPs ALPTP STLTP STL Link IP/UDP/RTP Microwave/Satellite/Fiber Preamble Information Timing & Mgt Information STLTP Broadcast Gateway ure 4.1 High-level overview of system configuration. one correspondence between individual Streams of ALP packets and epare ALP packets for Transmission, in the Broadcast Gateway, the ALP ed in Baseband Packets (BBPs), which have defined sizes that are ter (Kpayload) related to the specific characteristics of the particular PLP(s) arried. The sizes of the BBPs in a given Stream are set to assure that the e related PLP in a frame is filled by the BBPs derived from an associated LP packets either are segmented or are concatenated so that they fill the BBPs carrying them as completely as possible without overflowing the of data through the system, several buffers are required to hold data for ment of data emission. Buffering also is required in certain instances to e obtained from a data Stream and used to control particular functionality e corresponding data is processed further. Two specific instances of such stem. The first buffer inserts at least one Physical Layer frame of delay in PLP Demux SMPTE ST 2022-1 ECC Decoder SMPTE ST 2022-1 ECC Encoder Authentication STL Rcvr STL Xmtr IP UDP RTP IP UDP RTP IP UDP RTP IP UDP RTP IP Packetizers Baseband Packetizers PLPs PLPs Scheduler Timing & Mgt Generator Preamble Generator ALP Demux ALP Mux IP UDP RTP ALPs ALP Encapsulation ALPs Data Source Data Source Data Source Data Source ALP Payload (ALPTP) STL Payload (STLTP) IP (ROUTE/MMT), TS, Generic Data In DSTP Payloads o System Manager (BXF) To/From Data Sources (MDCoIP) STL Link IP/UDP/RTP Microwave/Satellite/Fiber ≤ 1 Phy Frame Delay (≤ 5secs) ALP Buffers ALPs LLS Ind. Configuration Mgr STL Payload (STLTP) EAS Trig. Broadcast Gateway w/External ALP Gen Broadcast Gateway w/Internal ALP Gen IP UDP RTP PLP Mux PLPs USB Crypto Token Security Device Security Data Processor Security Data Stream PLPs Authentication USB Crypto Token Security Device Security Data Processor Keys Security Data Stream Keys Figure 4.2 System architecture. Figure 4.2 shows a possible system architecture; other configurations are possible. Wh nsidering system configurations, data rates and interfaces between functional blocks must ken into account in developing practical implementations. System Manager onfiguration aspects of the overall system are controlled by a single entity called a Syste P SMPTE ST 2022-1 ECC Decoder SMPTE ST 2022-1 ECC Encoder Authentication STL Rcvr STL Xmtr IP UDP RTP IP UDP RTP IP UDP RTP IP UDP RTP IP Packetizers Baseband Packetizers PLPs PLPs Scheduler Timing & Mgt Generator Preamble Generator ALP Demux ALP Mux IP UDP RTP ALPs ALP Encapsulation ALPs Data Source Data Source Data Source Data Source ALP Payload (ALPTP) STL Payload (STLTP) IP (ROUTE/MMT), TS, Generic Data In DSTP Payloads From/To System Manager (BXF) To/From Data Sources (MDCoIP) STL Link IP/UDP/RTP Microwave/Satellite/Fiber ≤ 1 Phy Frame Delay (≤ 5secs) ALP Buffers ALPs LLS Ind. Configuration Mgr STL Payload (STLTP) EAS Trig. Broadcast Gateway w/External ALP Gen Broadcast Gateway w/Internal ALP Gen IP UDP RTP PLP Mux PLPs USB Crypto Token Security Device Security Data Processor Security Data Stream S Keys Figure 4.2 System architecture. Figure 4.2 shows a possible system architecture; other configurations are poss considering system configurations, data rates and interfaces between functional bloc taken into account in developing practical implementations. System Manager Configuration aspects of the overall system are controlled by a single entity calle PLP Demux SMPTE ST 2022-1 ECC Decoder SMPTE ST 2022-1 ECC Encoder Authentication STL Rcvr STL Xmtr IP UDP RTP IP UDP RTP IP UDP RTP IP UDP RTP IP Packetizers Baseband Packetizers PLPs PLPs Scheduler Timing & Mgt Generator Preamble Generator ALP Demux ALP Mux IP UDP RTP ALPs ALP Encapsulation ALPs Data Source Data Source Data Source Data Source ALP Payload (ALPTP) STL Payload (STLTP) IP (ROUTE/MMT), TS, Generic Data In DSTP Payloads o System Manager (BXF) To/From Data Sources (MDCoIP) STL Link IP/UDP/RTP Microwave/Satellite/Fiber ≤ 1 Phy Frame Delay (≤ 5secs) ALP Buffers ALPs LLS Ind. Configuration Mgr STL Payload (STLTP) EAS Trig. Broadcast Gateway w/External ALP Gen Broadcast Gateway w/Internal ALP Gen IP UDP RTP PLP Mux PLPs USB Crypto Token Security Device Security Data Processor Security Data Stream PLPs Authentication USB Crypto Token Security Device Security Data Processor Keys Security Data Stream Keys Figure 4.2 System architecture. Figure 4.2 shows a possible system architecture; other configurations are possible. Wh nsidering system configurations, data rates and interfaces between functional blocks must ken into account in developing practical implementations. System Manager PLP Demux SMPTE ST 2022-1 ECC Decoder SMPTE ST 2022-1 ECC Encoder Authentication STL Rcvr STL Xmtr IP UDP RTP IP UDP RTP IP UDP RTP IP UDP RTP IP Packetizers Baseband Packetizers PLPs PLPs Scheduler Timing & Mgt Generator Preamble Generator ALP Demux ALP Mux IP UDP RTP ALPs ALP Encapsulation ALPs Data Source Data Source Data Source Data Source ALP Payload (ALPTP) STL Payload (STLTP) IP (ROUTE/MMT), TS, Generic Data In DSTP Payloads o System Manager (BXF) To/From Data Sources (MDCoIP) STL Link IP/UDP/RTP Microwave/Satellite/Fiber ≤ 1 Phy Frame Delay (≤ 5secs) ALP Buffers ALPs LLS Ind. Configuration Mgr STL Payload (STLTP) EAS Trig. Broadcast Gateway w/External ALP Gen Broadcast Gateway w/Internal ALP Gen IP UDP RTP PLP Mux PLPs USB Crypto Token Security Device Security Data Processor Security Data Stream PLPs Authentication USB Crypto Token Security Device Security Data Processor Keys Security Data Stream Keys Figure 4.2 System architecture. Figure 4.2 shows a possible system architecture; other configurations are possible. Wh nsidering system configurations, data rates and interfaces between functional blocks must ken into account in developing practical implementations. System Manager onfiguration aspects of the overall system are controlled by a single entity called a Syste PLP Demux SMPTE ST 2022-1 ECC Decoder SMPTE ST 2022-1 ECC Encoder Authentication STL Rcvr STL Xmtr IP UDP RTP IP UDP RTP IP UDP RTP IP UDP RTP IP Packetizers Baseband Packetizers PLPs PLPs Scheduler Timing & Mgt Generator Preamble Generator ALP Demux ALP Mux IP UDP RTP ALPs ALP Encapsulation ALPs Data Source Data Source Data Source Data Source ALP Payload (ALPTP) STL Payload (STLTP) IP (ROUTE/MMT), TS, Generic Data In DSTP Payloads o System Manager (BXF) To/From Data Sources (MDCoIP) STL Link IP/UDP/RTP Microwave/Satellite/Fiber ≤ 1 Phy Frame Delay (≤ 5secs) ALP Buffers ALPs LLS Ind. Configuration Mgr STL Payload (STLTP) EAS Trig. Broadcast Gateway w/External ALP Gen Broadcast Gateway w/Internal ALP Gen IP UDP RTP PLP Mux PLPs USB Crypto Token Security Device Security Data Processor Security Data Stream PLPs Authentication USB Crypto Token Security Device Security Data Processor Keys Security Data Stream Keys Figure 4.2 System architecture. Figure 4.2 shows a possible system architecture; other configurations are possible. Wh nsidering system configurations, data rates and interfaces between functional blocks must ken into account in developing practical implementations. System Manager onfiguration aspects of the overall system are controlled by a single entity called a Syste PLP Demux SMPTE ST 2022-1 ECC Decoder SMPTE ST 2022-1 ECC Encoder Authentication STL Rcvr STL Xmtr IP UDP RTP IP UDP RTP IP UDP RTP IP UDP RTP IP Packetizers Baseband Packetizers PLPs PLPs Scheduler Timing & Mgt Generator Preamble Generator ALP Demux ALP Mux IP UDP RTP ALPs ALP Encapsulation ALPs Data Source Data Source Data Source Data Source ALP Payload (ALPTP) STL Payload (STLTP) IP (ROUTE/MMT), TS, Generic Data In DSTP Payloads o System Manager (BXF) To/From Data Sources (MDCoIP) STL Link IP/UDP/RTP Microwave/Satellite/Fiber ≤ 1 Phy Frame Delay (≤ 5secs) ALP Buffers ALPs LLS Ind. Configuration Mgr STL Payload (STLTP) EAS Trig. Broadcast Gateway w/External ALP Gen Broadcast Gateway w/Internal ALP Gen IP UDP RTP PLP Mux PLPs USB Crypto Token Security Device Security Data Processor Security Data Stream PLPs Authentication USB Crypto Token Security Device Security Data Processor Keys Security Data Stream Keys Figure 4.2 System architecture. Figure 4.2 shows a possible system architecture; other configurations are possible. Wh nsidering system configurations, data rates and interfaces between functional blocks must ken into account in developing practical implementations. System Manager PLP Demux SMPTE ST 2022-1 ECC Decoder SMPTE ST 2022-1 ECC Encoder Authentication STL Rcvr STL Xmtr IP UDP RTP IP UDP RTP IP UDP RTP IP UDP RTP IP Packetizers Baseband Packetizers PLPs PLPs Scheduler Timing & Mgt Generator Preamble Generator ALP Demux ALP Mux IP UDP RTP ALPs ALP Encapsulation ALPs Data Source Data Source Data Source Data Source ALP Payload (ALPTP) STL Payload (STLTP) IP (ROUTE/MMT), TS, Generic Data In DSTP Payloads (BXF) To/From Data Sources (MDCoIP) STL Link IP/UDP/RTP Microwave/Satellite/Fiber ≤ 1 Phy Frame Delay (≤ 5secs) ALP Buffers ALPs LLS Ind. STL Payload (STLTP) EAS Trig. w/External ALP Gen w/Internal ALP Gen IP UDP RTP PLP Mux PLPs USB Crypto Token Security Device Security Data Processor Security Data Stream PLPs Authenticatio USB Crypto Token Security Device Security Data Processor Keys Security Data Stream Keys Figure 4.2 System architecture. Figure 4.2 shows a possible system architecture; other configurations are possible. W nsidering system configurations, data rates and interfaces between functional blocks must en into account in developing practical implementations. System Manager nfiguration aspects of the overall system are controlled by a single entity called a Sys anager, which is represented in Figure 4.2 only as a connection to the Configuration Manage PLP Demux SMPTE ST 2022-1 ECC Decoder SMPTE ST 2022-1 ECC Encoder entication STL Rcvr STL Xmtr IP UDP RTP IP UDP RTP IP UDP RTP IP UDP RTP iming & Mgt enerator STL Payload (STLTP) STL Link IP/UDP/RTP Microwave/Satellite/Fiber STL Payload (STLTP) w/External ALP Gen PLP Mux PLPs USB Crypto Token Security Device Security Data Processor Security Data Stream PLPs Authentication USB Crypto Token Security Device Security Data Processor Keys Security Data Stream Keys ystem architecture. hitecture; other configurations are possible. When and interfaces between functional blocks must be lementations. are controlled by a single entity called a System nly as a connection to the Configuration Manager in an be anything from a web-page based setup screen Korean Broadcasting System | Broadcast Technical Research Institute Bit Int’l FEC Mapper LDM MIMO Time Int’l OFDM Framer/ Preamble Inserter Freq Int’l Pilot/ Tone Reserve MISO IFFT PAPR GI ≤ 1sec Network Comp. Buffers PLPs PLPs PLPs PLPs PLPs PLPs PLPs PHY Fr PHY Fr PHY Fr PHY Fr PHY Fr PHY Fr SMPTE ST 2022-1 ECC Decoder SMPTE ST 2022-1 ECC Encoder Authentication STL Rcvr STL Xmtr IP UDP RTP IP UDP RTP IP UDP RTP IP UD RT IP Packetizers Baseband Packetizers PLPs PLPs Scheduler Timing & Mgt Generator Preamble Generator ALP Demux ALP Mux IP UDP RTP ALPs ALP Encapsulation ALPs Data Source Data Source Data Source Data Source Scrambler PLPs ALP Payload (ALPTP) STL Payload (STLTP) IP (ROUTE/MMT), TS, Generic Data In DSTP Payloads From/To System Manager (BXF) To/From Data Sources (MDCoIP) STL Link IP/UDP/RTP Microwave/Satellite/Fiber ≤ 1 Phy Frame Delay (≤ 5secs) ALP Buffers ALPs LLS Ind. Configuration Mgr ST Paylo (STL EAS Trig. Broadcast Gateway w/External ALP Gen Broadcast Gateway w/Internal ALP Gen IP UDP RTP PLP Mux PLPs USB Crypto Token Security Device Security Data Processor Security Data Stream Keys Figure 4.2 System architecture. Figure 4.2 shows a possible system architecture; other configurations are po Bit Int’l FEC Mapper LDM MIMO Time Int’l OFDM Framer/ Preamble Inserter Freq Int’l Pilot/ Tone Reserve MISO IFFT ≤ 1sec Network Comp. Buffers Preamble Parser PLPs PLPs PLPs PLPs PLPs PLPs PLPs PHY Fr PHY Fr PHY Fr PHY Fr SMPTE ST 2022-1 ECC Encoder Authentication STL Xmtr IP UDP RTP IP UDP RTP IP Packetizers Baseband Packetizers PLPs PLPs Scheduler Timing & Mgt Generator Preamble Generator ALP Demux ALP Mux IP UDP RTP ALPs ALP Encapsulation ALPs Data Source Data Source Data Source Data Source Scrambler PLPs ALP Payload (ALPTP) STL Payload (STLTP) IP (ROUTE/MMT), TS, Generic Data In DSTP Payloads From/To System Manager (BXF) To/From Data Sources (MDCoIP) STL Link IP/UDP/RTP Microwave/Satellite/Fiber ≤ 1 Phy Frame Delay (≤ 5secs) ALP Buffers ALPs LLS Ind. Configuration Mgr EAS Trig. Broadcast Gateway w/External ALP Gen Broadcast Gateway w/Internal ALP Gen IP UDP RTP PLP Mux PLPs USB Crypto Token Security Device Security Data Processor Security Data Stream Keys Figure 4.2 System architecture. Figure 4.2 shows a possible system architecture; other configuratio Bit Int’l FEC Mapper LDM MIMO Time Int’l OFDM Framer/ Preamble Inserter Freq Int’l Pilot/ Tone Reserve MISO IFFT PAPR G ≤ 1sec Network Comp. Buffers Preamble Parser PLPs PLPs PLPs PLPs PLPs PLPs PLPs PHY Fr PHY Fr PHY Fr PHY Fr PHY Fr PHY Fr SMPTE ST 2022-1 ECC Decoder SMPTE ST 2022-1 ECC Encoder Authentication STL Rcvr STL Xmtr IP UDP RTP IP UDP RTP IP UDP RTP U R IP Packetizers Baseband Packetizers PLPs PLPs Scheduler Timing & Mgt Generator Preamble Generator ALP Demux ALP Mux IP UDP RTP ALPs ALP Encapsulation ALPs Data Source Data Source Data Source Data Source Scrambler PLPs ALP Payload (ALPTP) STL Payload (STLTP) IP (ROUTE/MMT), TS, Generic Data In DSTP Payloads From/To System Manager (BXF) To/From Data Sources (MDCoIP) STL Link IP/UDP/RTP Microwave/Satellite/Fiber ≤ 1 Phy Frame Delay (≤ 5secs) ALP Buffers ALPs LLS Ind. Configuration Mgr S Pay (ST EAS Trig. Broadcast Gateway w/External ALP Gen Broadcast Gateway w/Internal ALP Gen IP UDP RTP PLP Mux PLPs USB Crypto Token Security Device Security Data Processor Security Data Stream Keys Figure 4.2 System architecture. Bit Int’l FEC Mapper LDM MIMO Time Int’l OFDM Framer/ Preamble Inserter Freq Int’l Pilot/ Tone Reserve MISO IFFT PAPR G ≤ 1sec Network Comp. Buffers PLPs PLPs PLPs PLPs PLPs PLPs PLPs PHY Fr PHY Fr PHY Fr PHY Fr PHY Fr PHY Fr SMPTE ST 2022-1 ECC Decoder SMPTE ST 2022-1 ECC Encoder Authentication STL Rcvr STL Xmtr IP UDP RTP IP UDP RTP IP UDP RTP U R IP Packetizers Baseband Packetizers PLPs PLPs Scheduler Timing & Mgt Generator Preamble Generator ALP Demux ALP Mux IP UDP RTP ALPs ALP Encapsulation ALPs Data Source Data Source Data Source Data Source Scrambler PLPs ALP Payload (ALPTP) STL Payload (STLTP) IP (ROUTE/MMT), TS, Generic Data In DSTP Payloads From/To System Manager (BXF) To/From Data Sources (MDCoIP) STL Link IP/UDP/RTP Microwave/Satellite/Fiber ≤ 1 Phy Frame Delay (≤ 5secs) ALP Buffers ALPs LLS Ind. Configuration Mgr S Pay (ST EAS Trig. Broadcast Gateway w/External ALP Gen Broadcast Gateway w/Internal ALP Gen IP UDP RTP PLP Mux PLPs USB Crypto Token Security Device Security Data Processor Security Data Stream Keys Figure 4.2 System architecture. Figure 4.2 shows a possible system architecture; other configurations are po Bit Int’l FEC Mapper LDM MIMO Time Int’l OFDM Framer/ Preamble Inserter Freq Int’l Pilot/ Tone Reserve MISO IFFT PAPR G ≤ 1sec Network Comp. Buffers PLPs PLPs PLPs PLPs PLPs PLPs PLPs PHY Fr PHY Fr PHY Fr PHY Fr PHY Fr PHY Fr SMPTE ST 2022-1 ECC Decoder SMPTE ST 2022-1 ECC Encoder Authentication STL Rcvr STL Xmtr IP UDP RTP IP UDP RTP IP UDP RTP U R IP Packetizers Baseband Packetizers PLPs PLPs Scheduler Timing & Mgt Generator Preamble Generator ALP Demux ALP Mux IP UDP RTP ALPs ALP Encapsulation ALPs Data Source Data Source Data Source Data Source Scrambler PLPs ALP Payload (ALPTP) STL Payload (STLTP) IP (ROUTE/MMT), TS, Generic Data In DSTP Payloads From/To System Manager (BXF) To/From Data Sources (MDCoIP) STL Link IP/UDP/RTP Microwave/Satellite/Fiber ≤ 1 Phy Frame Delay (≤ 5secs) ALP Buffers ALPs LLS Ind. Configuration Mgr S Pay (ST EAS Trig. Broadcast Gateway w/External ALP Gen Broadcast Gateway w/Internal ALP Gen IP UDP RTP PLP Mux PLPs USB Crypto Token Security Device Security Data Processor Security Data Stream Keys Figure 4.2 System architecture. Figure 4.2 shows a possible system architecture; other configurations are po Korean Broadcasting System | Broadcast Technical Research Institute Bit Int’l FEC Mapper LDM MIMO Time Int’l OFDM Framer/ Preamble Inserter Freq Int’l Pilot/ Tone Reserve MISO IFFT PAPR ≤ 1sec Network Comp. Buffers PLPs PLPs PLPs PLPs PLPs PLPs PLPs PHY Fr PHY Fr PHY Fr PHY Fr PHY Fr PHY Fr SMPTE ST 2022-1 ECC Decoder SMPTE ST 2022-1 ECC Encoder Authentication STL Rcvr STL Xmtr IP UDP RTP IP UDP RTP IP UDP RTP IP Packetizers Baseband Packetizers PLPs PLPs Scheduler Timing & Mgt Generator Preamble Generator ALP Demux ALP Mux IP UDP RTP ALPs ALP Encapsulation ALPs Data Source Data Source Data Source Data Source Scrambler PLPs ALP Payload (ALPTP) STL Payload (STLTP) IP (ROUTE/MMT), TS, Generic Data In DSTP Payloads From/To System Manager (BXF) To/From Data Sources (MDCoIP) STL Link IP/UDP/RTP Microwave/Satellite/Fiber ≤ 1 Phy Frame Delay (≤ 5secs) ALP Buffers ALPs LLS Ind. Configuration Mgr EAS Trig. Broadcast Gateway w/External ALP Gen Broadcast Gateway w/Internal ALP Gen IP UDP RTP PLP Mux PLPs USB Crypto Token Security Device Security Data Processor Security Data Stream Keys Figure 4.2 System architecture. Figure 4.2 shows a possible system architecture; other configurations are p Bit Int’l FEC Mapper LDM MIMO Time Int’l OFDM Framer/ Preamble Inserter Freq Int’l Pilot/ Tone Reserve MISO ≤ 1sec Network Comp. Buffers Preamble Parser PLPs PLPs PLPs PLPs PLPs PLPs PLPs PHY Fr PHY Fr PHY Fr PHY Fr SMPTE ST 2022-1 ECC Encoder Authentication STL Xmtr IP UDP RTP IP UDP RTP IP Packetizers Baseband Packetizers PLPs PLPs Scheduler Timing & Mgt Generator Preamble Generator ALP Demux ALP Mux IP UDP RTP ALPs ALP Encapsulation ALPs Data Source Data Source Data Source Data Source Scrambler PLPs ALP Payload (ALPTP) STL Payload (STLTP) IP (ROUTE/MMT), TS, Generic Data In DSTP Payloads From/To System Manager (BXF) To/From Data Sources (MDCoIP) STL Link IP/UDP/RTP Microwave/Satellite/Fib ≤ 1 Phy Frame Delay (≤ 5secs) ALP Buffers ALPs LLS Ind. Configuration Mgr EAS Trig. Broadcast Gateway w/External ALP Gen Broadcast Gateway w/Internal ALP Gen IP UDP RTP PLP Mux PLPs USB Crypto Token Security Device Security Data Processor Security Data Stream Keys Figure 4.2 System architecture. Figure 4.2 shows a possible system architecture; other configurati Bit Int’l FEC Mapper LDM MIMO Time Int’l OFDM Framer/ Preamble Inserter Freq Int’l Pilot/ Tone Reserve MISO IFFT PAPR ≤ 1sec Network Comp. Buffers Preamble Parser PLPs PLPs PLPs PLPs PLPs PLPs PLPs PHY Fr PHY Fr PHY Fr PHY Fr PHY Fr PHY Fr SMPTE ST 2022- ECC Decode SMPTE ST 2022-1 ECC Encoder Authentication STL Rcvr STL Xmtr IP UDP RTP IP UDP RTP IP UDP RTP IP Packetizers Baseband Packetizers PLPs PLPs Scheduler Timing & Mgt Generator Preamble Generator ALP Demux ALP Mux IP UDP RTP ALPs ALP Encapsulation ALPs Data Source Data Source Data Source Data Source Scrambler PLPs ALP Payload (ALPTP) STL Payload (STLTP) IP (ROUTE/MMT), TS, Generic Data In DSTP Payloads From/To System Manager (BXF) To/From Data Sources (MDCoIP) STL Link IP/UDP/RTP Microwave/Satellite/Fiber ≤ 1 Phy Frame Delay (≤ 5secs) ALP Buffers ALPs LLS Ind. Configuration Mgr EAS Trig. Broadcast Gateway w/External ALP Gen Broadcast Gateway w/Internal ALP Gen IP UDP RTP PLP Mux PLPs USB Crypto Token Security Device Security Data Processor Security Data Stream Keys Figure 4.2 System architecture. Bit Int’l FEC Mapper LDM MIMO Time Int’l OFDM Framer/ Preamble Inserter Freq Int’l Pilot/ Tone Reserve MISO IFFT PAPR ≤ 1sec Network Comp. Buffers PLPs PLPs PLPs PLPs PLPs PLPs PLPs PHY Fr PHY Fr PHY Fr PHY Fr PHY Fr PHY Fr SMPTE ST 2022- ECC Decode SMPTE ST 2022-1 ECC Encoder Authentication STL Rcvr STL Xmtr IP UDP RTP IP UDP RTP IP UDP RTP IP Packetizers Baseband Packetizers PLPs PLPs Scheduler Timing & Mgt Generator Preamble Generator ALP Demux ALP Mux IP UDP RTP ALPs ALP Encapsulation ALPs Data Source Data Source Data Source Data Source Scrambler PLPs ALP Payload (ALPTP) STL Payload (STLTP) IP (ROUTE/MMT), TS, Generic Data In DSTP Payloads From/To System Manager (BXF) To/From Data Sources (MDCoIP) STL Link IP/UDP/RTP Microwave/Satellite/Fiber ≤ 1 Phy Frame Delay (≤ 5secs) ALP Buffers ALPs LLS Ind. Configuration Mgr EAS Trig. Broadcast Gateway w/External ALP Gen Broadcast Gateway w/Internal ALP Gen IP UDP RTP PLP Mux PLPs USB Crypto Token Security Device Security Data Processor Security Data Stream Keys Figure 4.2 System architecture. Figure 4.2 shows a possible system architecture; other configurations are p Bit Int’l FEC Mapper LDM MIMO Time Int’l OFDM Framer/ Preamble Inserter Freq Int’l Pilot/ Tone Reserve MISO IFFT PAPR ≤ 1sec Network Comp. Buffers PLPs PLPs PLPs PLPs PLPs PLPs PLPs PHY Fr PHY Fr PHY Fr PHY Fr PHY Fr PHY Fr SMPTE ST 2022- ECC Decode SMPTE ST 2022-1 ECC Encoder Authentication STL Rcvr STL Xmtr IP UDP RTP IP UDP RTP IP UDP RTP IP Packetizers Baseband Packetizers PLPs PLPs Scheduler Timing & Mgt Generator Preamble Generator ALP Demux ALP Mux IP UDP RTP ALPs ALP Encapsulation ALPs Data Source Data Source Data Source Data Source Scrambler PLPs ALP Payload (ALPTP) STL Payload (STLTP) IP (ROUTE/MMT), TS, Generic Data In DSTP Payloads From/To System Manager (BXF) To/From Data Sources (MDCoIP) STL Link IP/UDP/RTP Microwave/Satellite/Fiber ≤ 1 Phy Frame Delay (≤ 5secs) ALP Buffers ALPs LLS Ind. Configuration Mgr EAS Trig. Broadcast Gateway w/External ALP Gen Broadcast Gateway w/Internal ALP Gen IP UDP RTP PLP Mux PLPs USB Crypto Token Security Device Security Data Processor Security Data Stream Keys Figure 4.2 System architecture. Figure 4.2 shows a possible system architecture; other configurations are p S D SMPTE ST 2022-1 ECC Encoder Authentication STL Rcvr STL Xmtr IP UDP RTP IP UDP RTP IP UDP RTP IP Packetizers Baseband Packetizers PLPs PLPs Scheduler Generator ALP Demux ALP Mux IP UDP RTP ALPs ALP Encapsulation ALPs Data Source Data Source Data Source Data Source ALP Payload (ALPTP) STL Payload (STLTP) IP (ROUTE/MMT), TS, Generic Data In DSTP Payloads STL Link IP/UDP/RTP Microwave/Satellite/Fiber ≤ 1 Phy Frame Delay (≤ 5secs) ALP Buffers ALPs EAS Trig. IP UDP RTP PLP Mux PLPs Processor Security Data Stream Keys Figure 4.2 System architecture. Figure 4.2 shows a possible system architecture; other configurations are considering system configurations, data rates and interfaces between functiona taken into account in developing practical implementations. System Manager Configuration aspects of the overall system are controlled by a single entity Manager, which is represented in Figure 4.2 only as a connection to the Configur the Broadcast Gateway. A System Manager can be anything from a web-page ba with manual data entry to a fully automated system; its scope is control of an o Bit Int’l FEC Mapper LDM MIMO Time Int’l OFDM Framer/ Preamble Inserter Freq Int’l Pilot/ Tone Reserve MISO IFFT PAPR ≤ 1sec Network Comp. Buffers Fr Fr Fr Fr Fr Fr SMP ST 20 EC Deco SMPTE ST 2022-1 ECC Encoder Authentication STL Rcvr STL Xmtr IP UDP RTP IP UDP RTP IP UDP RTP IP Packetizers Baseband Packetizers PLPs PLPs Scheduler Timing & Mgt Generator Preamble Generator ALP Demux ALP Mux IP UDP RTP ALPs ALP Encapsulation ALPs Data Source Data Source Data Source Data Source Scrambler ALP Payload (ALPTP) STL Payload (STLTP) IP (ROUTE/MMT), TS, Generic Data In DSTP Payloads From/To System Manager (BXF) To/From Data Sources (MDCoIP) STL Link IP/UDP/RTP Microwave/Satellite/Fiber ≤ 1 Phy Frame Delay (≤ 5secs) ALP Buffers ALPs LLS Ind. Configuration Mgr EAS Trig. Broadcast Gateway w/External ALP Gen Broadcast Gateway w/Internal ALP Gen IP UDP RTP PLP Mux PLPs USB Crypto Token Security Device Security Data Processor Security Data Stream Keys Figure 4.2 System architecture. ATSC 3.0 Gateway SMPTE 2022-1 FEC 적용 예시 (L,D)=(8,5) 전송률 증가율 = = 32.5% 8+5 40 5004 5002 239.255.9.30:5000 BGW Setting (STL)

Slide 1

Slide 1 text

Slide 2

Slide 2 text

Slide 3

Slide 3 text

Slide 4

Slide 4 text

Slide 5

Slide 5 text

Slide 6

Slide 6 text

Slide 7

Slide 7 text

Slide 8

Slide 8 text

Slide 9

Slide 9 text

Slide 10

Slide 10 text

Slide 11

Slide 11 text

Slide 12

Slide 12 text

Slide 13

Slide 13 text

Slide 14

Slide 14 text

Slide 15

Slide 15 text

Slide 16

Slide 16 text

Slide 17

Slide 17 text

Slide 18

Slide 18 text

Slide 19

Slide 19 text

Slide 20

Slide 20 text

Slide 21

Slide 21 text

Slide 22

Slide 22 text

Slide 23

Slide 23 text

Slide 24

Slide 24 text

Slide 25

Slide 25 text

Slide 26

Slide 26 text

Slide 27

Slide 27 text

Slide 28

Slide 28 text

Slide 29

Slide 29 text

Slide 30

Slide 30 text

Slide 31

Slide 31 text

Slide 32

Slide 32 text

Slide 33

Slide 33 text

Slide 34

Slide 34 text

Slide 35

Slide 35 text

Slide 36

Slide 36 text

Slide 37

Slide 37 text

Slide 38

Slide 38 text

Slide 39

Slide 39 text

Slide 40

Slide 40 text