Slide 160
Slide 160 text
STL-FEC 기능 덕분에 STLTP 패킷 한 두개 깨져서는 송신기에 영향을 주지 않음.
45
Multiplexer
Various UDP/IP Streams
BBF, Timing, Control, etc.
FEC Encoder Transmitter
FEC Row
RTP/UDP/IP Stream
FEC Column
RTP/UDP/IP Stream
STL
Receiver
8
SMPTE 2022-1
FEC Decoder
9
IP Content Tunnel
SMPTE ST 2022-1
RTP/UDP/IP Stream
FEC Row
RTP/UDP/IP Stream
FEC Column
RTP/UDP/IP Stream
10
IP Tunnel
RTP/UDP/IP Stream
w/ Fixed Packet Size
PLP
Demultiplexer
11
Various UDP/IP Streams
BBF, Timing, Control, etc.
12 13
Figure 8.1 STL Transmission diagram.
The following paragraphs describe each of the call-outs, (1) through (13), in Figure 8.1. Items
(1) through (5) are further detailed in the FEC Encoding Process Section 8.5.1 below.
1) The multiple paths represent the RTP/UDP/IP Streams that are generated for each PLP as
described in Sections 8.2, 8.3, and 8.3.4. These are referred to as the Tunneled Packet
Streams.
2) The PLP Mux is configured to accept packets from multiple RTP/UDP/IP multicast
Streams to be tunneled.
3) The Tunneled Packets are grouped into fixed-size payloads to accommodate the SMPTE
ST 2022-1 FEC process [8]. The STLTP RTP fields are defined to allow the Tunneled
Packet Streams to be easily recovered and forwarded (refer to Section 8.6 below). The
fixed packet size of the ST 2022-1 packets is not defined by this standard and is assumed
to be configurable. It is expected that the packet size is within the typical 1500 MTU byte
range limit. Note that the larger the packets the longer the latency when performing FEC
Transmitter 1
Transmitter 2
Transmitter 3
ATSC A/324:2018 Scheduler / Studio to Transmitter Link 5 January 2018
payloads for easy reconstruction on the Data Consumer side. All other aspects of ST 2022-1 remain
identical to the capabilities described in [8] including support for any FEC constraints detailed in
Section 8 of that standard.
Note that latency will be longer with larger packet lengths.
8.5 STL Transmission Protocol Design
Figure 8.1 provides a detailed diagram of the portion of the broadcast Physical Layer chain
described by this section. Refer to Figure 4.2 for a complete diagram of the system architecture.
PLP
Multiplexer
Various UDP/IP Streams
BBF, Timing, Control, etc.
SMPTE 2022-1
FEC Encoder
IP Tunnel
RTP/UDP/IP Stream
w/ Fixed Packet Size
STL
Transmitter
IP Content Tunnel
SM PTE ST 2022-1
RTP/UDP/IP Stream
FEC Row
RTP/UDP/IP Stream
FEC Column
RTP/UDP/IP Stream
1 2
3
4
5
6 7 STL
STL
Receiver
8
SM PTE 2022-1
FEC Decoder
9
IP Content Tunnel
SMPTE ST 2022-1
RTP/UDP/IP Stream
FEC Row
RTP/UDP/IP Stream
FEC Column
RTP/UDP/IP Stream
10
IP Tunnel
RTP/UDP/IP Stream
w/ Fixed Packet Size
PLP
Demultiplexer
11
Various UDP/IP Streams
BBF, Timing, Control, etc.
12 13
Figure 8.1 STL Transmission diagram.
The following paragraphs describe each of the call-outs, (1) through (13), in Figure 8.1. Items
(1) through (5) are further detailed in the FEC Encoding Process Section 8.5.1 below.
1) The multiple paths represent the RTP/UDP/IP Streams that are generated for each PLP as
described in Sections 8.2, 8.3, and 8.3.4. These are referred to as the Tunneled Packet
Streams.
PLP Demux
SMPTE
ST 2022-1
ECC
Decoder
SMPTE
ST 2022-1
ECC
Encoder
Authentication STL Rcvr
STL Xmtr
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
IP
Packetizers
Baseband
Packetizers
PLPs
PLPs
Scheduler
Timing
& Mgt
Generator
Preamble
Generator
ALP
Demux
ALP
Mux
IP
UDP
RTP
ALPs
ALP
Encapsulation
ALPs
Data Source
Data Source
Data Source
Data Source
ALP
Payload
(ALPTP)
STL
Payload
(STLTP)
IP (ROUTE/MMT),
TS, Generic Data
In DSTP Payloads
To System Manager
(BXF)
To/From
Data Sources
(MDCoIP)
STL Link
IP/UDP/RTP
Microwave/Satellite/Fiber
≤ 1 Phy
Frame
Delay
(≤ 5secs)
ALP
Buffers
ALPs
LLS Ind.
Configuration
Mgr
STL
Payload
(STLTP)
EAS Trig.
Broadcast
Gateway
w/External
ALP Gen
Broadcast
Gateway
w/Internal
ALP Gen
IP
UDP
RTP
PLP Mux
PLPs
USB
Crypto
Token
Security
Device
Security
Data
Processor
Security
Data
Stream
PLPs
Authentication
USB
Crypto
Token
Security
Device
Security
Data
Processor
Keys
Security Data Stream
Keys
Figure 4.2 System architecture.
Figure 4.2 shows a possible system architecture; other configurations are possible. When
nsidering system configurations, data rates and interfaces between functional blocks must be
ken into account in developing practical implementations.
System Manager
onfiguration aspects of the overall system are controlled by a single entity called a System
PLP De
SMPTE
ST 2022-1
ECC
Decoder
SMPTE
ST 2022-1
ECC
Encoder
Authentication STL Rcvr
STL Xmtr
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
IP
Packetizers
Baseband
Packetizers
PLPs
PLPs
Scheduler
Timing
& Mgt
Generator
Preamble
Generator
ALP
Demux
ALP
Mux
IP
UDP
RTP
ALPs
ALP
Encapsulation
ALPs
Data Source
Data Source
Data Source
Data Source
ALP
Payload
(ALPTP)
STL
Payload
(STLTP)
IP (ROUTE/MMT),
TS, Generic Data
In DSTP Payloads
From/To System Manager
(BXF)
To/From
Data Sources
(MDCoIP)
STL Link
IP/UDP/RTP
Microwave/Satellite/Fiber
≤ 1 Phy
Frame
Delay
(≤ 5secs)
ALP
Buffers
ALPs
LLS Ind.
Configuration
Mgr
STL
Payload
(STLTP)
EAS Trig.
Broadcast
Gateway
w/External
ALP Gen
Broadcast
Gateway
w/Internal
ALP Gen
IP
UDP
RTP
PLP Mux
PLPs
USB
Crypto
Token
Security
Device
Security
Data
Processor
Security
Data
Stream
Securit
Keys
Figure 4.2 System architecture.
Figure 4.2 shows a possible system architecture; other configurations are possib
considering system configurations, data rates and interfaces between functional block
taken into account in developing practical implementations.
System Manager
Configuration aspects of the overall system are controlled by a single entity called
PLP Demux
SMPTE
ST 2022-1
ECC
Decoder
SMPTE
ST 2022-1
ECC
Encoder
Authentication STL Rcvr
STL Xmtr
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
IP
Packetizers
Baseband
Packetizers
PLPs
PLPs
Scheduler
Timing
& Mgt
Generator
Preamble
Generator
ALP
Demux
ALP
Mux
IP
UDP
RTP
ALPs
ALP
Encapsulation
ALPs
Data Source
Data Source
Data Source
Data Source
ALP
Payload
(ALPTP)
STL
Payload
(STLTP)
IP (ROUTE/MMT),
TS, Generic Data
In DSTP Payloads
o System Manager
(BXF)
To/From
Data Sources
(MDCoIP)
STL Link
IP/UDP/RTP
Microwave/Satellite/Fiber
≤ 1 Phy
Frame
Delay
(≤ 5secs)
ALP
Buffers
ALPs
LLS Ind.
Configuration
Mgr
STL
Payload
(STLTP)
EAS Trig.
Broadcast
Gateway
w/External
ALP Gen
Broadcast
Gateway
w/Internal
ALP Gen
IP
UDP
RTP
PLP Mux
PLPs
USB
Crypto
Token
Security
Device
Security
Data
Processor
Security
Data
Stream
PLPs
Authentication
USB
Crypto
Token
Security
Device
Security
Data
Processor
Keys
Security Data Stream
Keys
Figure 4.2 System architecture.
Figure 4.2 shows a possible system architecture; other configurations are possible. Whe
nsidering system configurations, data rates and interfaces between functional blocks must b
ken into account in developing practical implementations.
System Manager
onfiguration aspects of the overall system are controlled by a single entity called a System
PLP Demux
SMPTE
ST 2022-1
ECC
Decoder
SMPTE
ST 2022-1
ECC
Encoder
Authentication STL Rcvr
STL Xmtr
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
IP
Packetizers
Baseband
Packetizers
PLPs
PLPs
Scheduler
Timing
& Mgt
Generator
Preamble
Generator
ALP
Demux
ALP
Mux
IP
UDP
RTP
ALPs
ALP
Encapsulation
ALPs
Data Source
Data Source
Data Source
Data Source
ALP
Payload
(ALPTP)
STL
Payload
(STLTP)
IP (ROUTE/MMT),
TS, Generic Data
In DSTP Payloads
o System Manager
(BXF)
To/From
Data Sources
(MDCoIP)
STL Link
IP/UDP/RTP
Microwave/Satellite/Fiber
≤ 1 Phy
Frame
Delay
(≤ 5secs)
ALP
Buffers
ALPs
LLS Ind.
Configuration
Mgr
STL
Payload
(STLTP)
EAS Trig.
Broadcast
Gateway
w/External
ALP Gen
Broadcast
Gateway
w/Internal
ALP Gen
IP
UDP
RTP
PLP Mux
PLPs
USB
Crypto
Token
Security
Device
Security
Data
Processor
Security
Data
Stream
PLPs
Authentication
USB
Crypto
Token
Security
Device
Security
Data
Processor
Keys
Security Data Stream
Keys
Figure 4.2 System architecture.
Figure 4.2 shows a possible system architecture; other configurations are possible. Whe
nsidering system configurations, data rates and interfaces between functional blocks must b
ken into account in developing practical implementations.
System Manager
onfiguration aspects of the overall system are controlled by a single entity called a System
PLP Demux
SMPTE
ST 2022-1
ECC
Decoder
SMPTE
ST 2022-1
ECC
Encoder
Authentication STL Rcvr
STL Xmtr
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
IP
Packetizers
Baseband
Packetizers
PLPs
PLPs
Scheduler
Timing
& Mgt
Generator
Preamble
Generator
ALP
Demux
ALP
Mux
IP
UDP
RTP
ALPs
ALP
Encapsulation
ALPs
Data Source
Data Source
Data Source
Data Source
ALP
Payload
(ALPTP)
STL
Payload
(STLTP)
IP (ROUTE/MMT),
TS, Generic Data
In DSTP Payloads
o System Manager
(BXF)
To/From
Data Sources
(MDCoIP)
STL Link
IP/UDP/RTP
Microwave/Satellite/Fiber
≤ 1 Phy
Frame
Delay
(≤ 5secs)
ALP
Buffers
ALPs
LLS Ind.
Configuration
Mgr
STL
Payload
(STLTP)
EAS Trig.
Broadcast
Gateway
w/External
ALP Gen
Broadcast
Gateway
w/Internal
ALP Gen
IP
UDP
RTP
PLP Mux
PLPs
USB
Crypto
Token
Security
Device
Security
Data
Processor
Security
Data
Stream
PLPs
Authentication
USB
Crypto
Token
Security
Device
Security
Data
Processor
Keys
Security Data Stream
Keys
Figure 4.2 System architecture.
Figure 4.2 shows a possible system architecture; other configurations are possible. Whe
nsidering system configurations, data rates and interfaces between functional blocks must b
ken into account in developing practical implementations.
System Manager
onfiguration aspects of the overall system are controlled by a single entity called a System
PLP Demux
SMPTE
ST 2022-1
ECC
Decoder
SMPTE
ST 2022-1
ECC
Encoder
Authentication STL Rcvr
STL Xmtr
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
IP
Packetizers
Baseband
Packetizers
PLPs
PLPs
Scheduler
Timing
& Mgt
Generator
Preamble
Generator
ALP
Demux
ALP
Mux
IP
UDP
RTP
ALPs
ALP
Encapsulation
ALPs
Data Source
Data Source
Data Source
Data Source
ALP
Payload
(ALPTP)
STL
Payload
(STLTP)
IP (ROUTE/MMT),
TS, Generic Data
In DSTP Payloads
o System Manager
(BXF)
To/From
Data Sources
(MDCoIP)
STL Link
IP/UDP/RTP
Microwave/Satellite/Fiber
≤ 1 Phy
Frame
Delay
(≤ 5secs)
ALP
Buffers
ALPs
LLS Ind.
Configuration
Mgr
STL
Payload
(STLTP)
EAS Trig.
Broadcast
Gateway
w/External
ALP Gen
Broadcast
Gateway
w/Internal
ALP Gen
IP
UDP
RTP
PLP Mux
PLPs
USB
Crypto
Token
Security
Device
Security
Data
Processor
Security
Data
Stream
PLPs
Authentication
USB
Crypto
Token
Security
Device
Security
Data
Processor
Keys
Security Data Stream
Keys
Figure 4.2 System architecture.
Figure 4.2 shows a possible system architecture; other configurations are possible. Whe
nsidering system configurations, data rates and interfaces between functional blocks must b
ken into account in developing practical implementations.
System Manager
PLP Demux
SMPTE
ST 2022-1
ECC
Decoder
SMPTE
ST 2022-1
ECC
Encoder
Authentication STL Rcvr
STL Xmtr
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
IP
Packetizers
Baseband
Packetizers
PLPs
PLPs
Scheduler
Timing
& Mgt
Generator
Preamble
Generator
ALP
Demux
ALP
Mux
IP
UDP
RTP
ALPs
ALP
Encapsulation
ALPs
Data Source
Data Source
Data Source
Data Source
ALP
Payload
(ALPTP)
STL
Payload
(STLTP)
IP (ROUTE/MMT),
TS, Generic Data
In DSTP Payloads
(BXF)
To/From
Data Sources
(MDCoIP)
STL Link
IP/UDP/RTP
Microwave/Satellite/Fiber
≤ 1 Phy
Frame
Delay
(≤ 5secs)
ALP
Buffers
ALPs
LLS Ind.
STL
Payload
(STLTP)
EAS Trig.
w/External
ALP Gen
w/Internal
ALP Gen
IP
UDP
RTP
PLP Mux
PLPs
USB
Crypto
Token
Security
Device
Security
Data
Processor
Security
Data
Stream
PLPs
Authentication
USB
Crypto
Token
Security
Device
Security
Data
Processor
Keys
Security Data Stream
Keys
Figure 4.2 System architecture.
Figure 4.2 shows a possible system architecture; other configurations are possible. Wh
nsidering system configurations, data rates and interfaces between functional blocks must
ken into account in developing practical implementations.
System Manager
nfiguration aspects of the overall system are controlled by a single entity called a Syste
anager, which is represented in Figure 4.2 only as a connection to the Configuration Manager
PLP Demux
SMPTE
ST 2022-1
ECC
Decoder
SMPTE
ST 2022-1
ECC
Encoder
hentication STL Rcvr
STL Xmtr
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
Timing
& Mgt
Generator
STL
Payload
(STLTP)
STL Link
IP/UDP/RTP
Microwave/Satellite/Fiber
STL
Payload
(STLTP)
ALP Gen
PLP Mux
PLPs
USB
Crypto
Token
Security
Device
Security
Data
Processor
Security
Data
Stream
PLPs
Authentication
USB
Crypto
Token
Security
Device
Security
Data
Processor
Keys
Security Data Stream
Keys
ystem architecture.
hitecture; other configurations are possible. When
and interfaces between functional blocks must be
plementations.
are controlled by a single entity called a System
nly as a connection to the Configuration Manager in
an be anything from a web-page based setup screen
Korean Broadcasting System | Broadcast Technical Research Institute
Bit Int’l
FEC Mapper LDM MIMO Time Int’l OFDM
Framer/
Preamble
Inserter
Freq Int’l Pilot/
Tone
Reserve
MISO IFFT PAPR GI Bootst
Spectr
Shap
≤ 1sec
Network
Comp.
Buffers
PLPs PLPs PLPs PLPs PLPs PLPs PLPs PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
PLP Demux
SMPTE
ST 2022-1
ECC
Decoder
SMPTE
ST 2022-1
ECC
Encoder
Authentication STL Rcvr
STL Xmtr
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
IP
Packetizers
Baseband
Packetizers
PLPs
PLPs
Scheduler
Timing
& Mgt
Generator
Preamble
Generator
ALP
Demux
ALP
Mux
IP
UDP
RTP
ALPs
ALP
Encapsulation
ALPs
Data Source
Data Source
Data Source
Data Source
Scrambler
PLPs
ALP
Payload
(ALPTP)
STL
Payload
(STLTP)
IP (ROUTE/MMT),
TS, Generic Data
In DSTP Payloads
From/To System Manager
(BXF)
To/From
Data Sources
(MDCoIP)
STL Link
IP/UDP/RTP
Microwave/Satellite/Fiber
≤ 1 Phy
Frame
Delay
(≤ 5secs)
ALP
Buffers
ALPs
LLS Ind.
Configuration
Mgr
STL
Payload
(STLTP)
EAS Trig.
Broadcast
Gateway
w/External
ALP Gen
Broadcast
Gateway
w/Internal
ALP Gen
IP
UDP
RTP
PLP Mux
PLPs
USB
Crypto
Token
Security
Device
Security
Data
Processor
Security
Data
Stream
PL
Securi
Da
Process
Security Data S
Keys
Figure 4.2 System architecture.
Figure 4.2 shows a possible system architecture; other configurations are possible
Bit Int’l
FEC Mapper LDM MIMO Time Int’l OFDM
Framer/
Preamble
Inserter
Freq Int’l Pilot/
Tone
Reserve
MISO IFFT PAPR
≤ 1sec
Network
Comp.
Buffers
Preamble
Parser
PLPs PLPs PLPs PLPs PLPs PLPs PLPs PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
SMPTE
ST 2022-1
ECC
Encoder
Authentication STL Rcvr
STL Xmtr
IP
UDP
RTP
IP
UDP
RTP
IP
UD
RT
IP
Packetizers
Baseband
Packetizers
PLPs
PLPs
Scheduler
Timing
& Mgt
Generator
Preamble
Generator
ALP
Demux
ALP
Mux
IP
UDP
RTP
ALPs
ALP
Encapsulation
ALPs
Data Source
Data Source
Data Source
Data Source
Scrambler
PLPs
ALP
Payload
(ALPTP)
STL
Payload
(STLTP)
IP (ROUTE/MMT),
TS, Generic Data
In DSTP Payloads
From/To System Manager
(BXF)
To/From
Data Sources
(MDCoIP)
STL Link
IP/UDP/RTP
Microwave/Satellite/Fiber
≤ 1 Phy
Frame
Delay
(≤ 5secs)
ALP
Buffers
ALPs
LLS Ind.
Configuration
Mgr
EAS Trig.
Broadcast
Gateway
w/External
ALP Gen
Broadcast
Gateway
w/Internal
ALP Gen
IP
UDP
RTP
PLP Mux
PLPs
USB
Crypto
Token
Security
Device
Security
Data
Processor
Security
Data
Stream
Keys
Figure 4.2 System architecture.
Figure 4.2 shows a possible system architecture; other configurations ar
Bit Int’l
FEC Mapper LDM MIMO Time Int’l OFDM
Framer/
Preamble
Inserter
Freq Int’l Pilot/
Tone
Reserve
MISO IFFT PAPR GI Boots
Spec
Sha
≤ 1sec
Network
Comp.
Buffers
Preamble
Parser
PLPs PLPs PLPs PLPs PLPs PLPs PLPs PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
PLP Demux
SMPTE
ST 2022-1
ECC
Decoder
SMPTE
ST 2022-1
ECC
Encoder
Authentication STL Rcvr
STL Xmtr
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
IP
Packetizers
Baseband
Packetizers
PLPs
PLPs
Scheduler
Timing
& Mgt
Generator
Preamble
Generator
ALP
Demux
ALP
Mux
IP
UDP
RTP
ALPs
ALP
Encapsulation
ALPs
Data Source
Data Source
Data Source
Data Source
Scrambler
PLPs
ALP
Payload
(ALPTP)
STL
Payload
(STLTP)
IP (ROUTE/MMT),
TS, Generic Data
In DSTP Payloads
From/To System Manager
(BXF)
To/From
Data Sources
(MDCoIP)
STL Link
IP/UDP/RTP
Microwave/Satellite/Fiber
≤ 1 Phy
Frame
Delay
(≤ 5secs)
ALP
Buffers
ALPs
LLS Ind.
Configuration
Mgr
STL
Payload
(STLTP)
EAS Trig.
Broadcast
Gateway
w/External
ALP Gen
Broadcast
Gateway
w/Internal
ALP Gen
IP
UDP
RTP
PLP Mux
PLPs
USB
Crypto
Token
Security
Device
Security
Data
Processor
Security
Data
Stream
P
Secu
D
Proces
Security Data
Keys
Figure 4.2 System architecture.
Bit Int’l
FEC Mapper LDM MIMO Time Int’l OFDM
Framer/
Preamble
Inserter
Freq Int’l Pilot/
Tone
Reserve
MISO IFFT PAPR GI Boots
Spec
Sha
≤ 1sec
Network
Comp.
Buffers
PLPs PLPs PLPs PLPs PLPs PLPs PLPs PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
PLP Demux
SMPTE
ST 2022-1
ECC
Decoder
SMPTE
ST 2022-1
ECC
Encoder
Authentication STL Rcvr
STL Xmtr
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
IP
Packetizers
Baseband
Packetizers
PLPs
PLPs
Scheduler
Timing
& Mgt
Generator
Preamble
Generator
ALP
Demux
ALP
Mux
IP
UDP
RTP
ALPs
ALP
Encapsulation
ALPs
Data Source
Data Source
Data Source
Data Source
Scrambler
PLPs
ALP
Payload
(ALPTP)
STL
Payload
(STLTP)
IP (ROUTE/MMT),
TS, Generic Data
In DSTP Payloads
From/To System Manager
(BXF)
To/From
Data Sources
(MDCoIP)
STL Link
IP/UDP/RTP
Microwave/Satellite/Fiber
≤ 1 Phy
Frame
Delay
(≤ 5secs)
ALP
Buffers
ALPs
LLS Ind.
Configuration
Mgr
STL
Payload
(STLTP)
EAS Trig.
Broadcast
Gateway
w/External
ALP Gen
Broadcast
Gateway
w/Internal
ALP Gen
IP
UDP
RTP
PLP Mux
PLPs
USB
Crypto
Token
Security
Device
Security
Data
Processor
Security
Data
Stream
P
Secu
D
Proces
Security Data
Keys
Figure 4.2 System architecture.
Figure 4.2 shows a possible system architecture; other configurations are possible
Bit Int’l
FEC Mapper LDM MIMO Time Int’l OFDM
Framer/
Preamble
Inserter
Freq Int’l Pilot/
Tone
Reserve
MISO IFFT PAPR GI Boots
Spec
Sha
≤ 1sec
Network
Comp.
Buffers
PLPs PLPs PLPs PLPs PLPs PLPs PLPs PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
PLP Demux
SMPTE
ST 2022-1
ECC
Decoder
SMPTE
ST 2022-1
ECC
Encoder
Authentication STL Rcvr
STL Xmtr
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
IP
Packetizers
Baseband
Packetizers
PLPs
PLPs
Scheduler
Timing
& Mgt
Generator
Preamble
Generator
ALP
Demux
ALP
Mux
IP
UDP
RTP
ALPs
ALP
Encapsulation
ALPs
Data Source
Data Source
Data Source
Data Source
Scrambler
PLPs
ALP
Payload
(ALPTP)
STL
Payload
(STLTP)
IP (ROUTE/MMT),
TS, Generic Data
In DSTP Payloads
From/To System Manager
(BXF)
To/From
Data Sources
(MDCoIP)
STL Link
IP/UDP/RTP
Microwave/Satellite/Fiber
≤ 1 Phy
Frame
Delay
(≤ 5secs)
ALP
Buffers
ALPs
LLS Ind.
Configuration
Mgr
STL
Payload
(STLTP)
EAS Trig.
Broadcast
Gateway
w/External
ALP Gen
Broadcast
Gateway
w/Internal
ALP Gen
IP
UDP
RTP
PLP Mux
PLPs
USB
Crypto
Token
Security
Device
Security
Data
Processor
Security
Data
Stream
P
Secu
D
Proces
Security Data
Keys
Figure 4.2 System architecture.
Figure 4.2 shows a possible system architecture; other configurations are possible
Korean Broadcasting System | Broadcast Technical Research Institute
Bit Int’l
FEC Mapper LDM MIMO Time Int’l OFDM
Framer/
Preamble
Inserter
Freq Int’l Pilot/
Tone
Reserve
MISO IFFT PAPR GI B
S
≤ 1sec
Network
Comp.
Buffers
PLPs PLPs PLPs PLPs PLPs PLPs PLPs PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
PLP Demu
SMPTE
ST 2022-1
ECC
Decoder
SMPTE
ST 2022-1
ECC
Encoder
Authentication STL Rcvr
STL Xmtr
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
IP
Packetizers
Baseband
Packetizers
PLPs
PLPs
Scheduler
Timing
& Mgt
Generator
Preamble
Generator
ALP
Demux
ALP
Mux
IP
UDP
RTP
ALPs
ALP
Encapsulation
ALPs
Data Source
Data Source
Data Source
Data Source
Scrambler
PLPs
ALP
Payload
(ALPTP)
STL
Payload
(STLTP)
IP (ROUTE/MMT),
TS, Generic Data
In DSTP Payloads
From/To System Manager
(BXF)
To/From
Data Sources
(MDCoIP)
STL Link
IP/UDP/RTP
Microwave/Satellite/Fiber
≤ 1 Phy
Frame
Delay
(≤ 5secs)
ALP
Buffers
ALPs
LLS Ind.
Configuration
Mgr
STL
Payload
(STLTP)
EAS Trig.
Broadcast
Gateway
w/External
ALP Gen
Broadcast
Gateway
w/Internal
ALP Gen
IP
UDP
RTP
PLP Mux
PLPs
USB
Crypto
Token
Security
Device
Security
Data
Processor
Security
Data
Stream
S
Pr
Security D
Keys
Figure 4.2 System architecture.
Figure 4.2 shows a possible system architecture; other configurations are possib
Bit Int’l
FEC Mapper LDM MIMO Time Int’l OFDM
Framer/
Preamble
Inserter
Freq Int’l Pilot/
Tone
Reserve
MISO IFFT
≤ 1sec
Network
Comp.
Buffers
Preamble
Parser
PLPs PLPs PLPs PLPs PLPs PLPs PLPs PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
SMPTE
ST 2022-1
ECC
Encoder
Authentication STL Rcvr
STL Xmtr
IP
UDP
RTP
IP
UDP
RTP
IP
Packetizers
Baseband
Packetizers
PLPs
PLPs
Scheduler
Timing
& Mgt
Generator
Preamble
Generator
ALP
Demux
ALP
Mux
IP
UDP
RTP
ALPs
ALP
Encapsulation
ALPs
Data Source
Data Source
Data Source
Data Source
Scrambler
PLPs
ALP
Payload
(ALPTP)
STL
Payload
(STLTP)
IP (ROUTE/MMT),
TS, Generic Data
In DSTP Payloads
From/To System Manager
(BXF)
To/From
Data Sources
(MDCoIP)
STL Link
IP/UDP/RTP
Microwave/Satellite/Fiber
≤ 1 Phy
Frame
Delay
(≤ 5secs)
ALP
Buffers
ALPs
LLS Ind.
Configuration
Mgr
EAS Trig.
Broadcast
Gateway
w/External
ALP Gen
Broadcast
Gateway
w/Internal
ALP Gen
IP
UDP
RTP
PLP Mux
PLPs
USB
Crypto
Token
Security
Device
Security
Data
Processor
Security
Data
Stream
Keys
Figure 4.2 System architecture.
Figure 4.2 shows a possible system architecture; other configurations
Bit Int’l
FEC Mapper LDM MIMO Time Int’l OFDM
Framer/
Preamble
Inserter
Freq Int’l Pilot/
Tone
Reserve
MISO IFFT PAPR GI
≤ 1sec
Network
Comp.
Buffers
Preamble
Parser
PLPs PLPs PLPs PLPs PLPs PLPs PLPs PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
PLP Dem
SMPTE
ST 2022-1
ECC
Decoder
SMPTE
ST 2022-1
ECC
Encoder
Authentication STL Rcvr
STL Xmtr
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
IP
Packetizers
Baseband
Packetizers
PLPs
PLPs
Scheduler
Timing
& Mgt
Generator
Preamble
Generator
ALP
Demux
ALP
Mux
IP
UDP
RTP
ALPs
ALP
Encapsulation
ALPs
Data Source
Data Source
Data Source
Data Source
Scrambler
PLPs
ALP
Payload
(ALPTP)
STL
Payload
(STLTP)
IP (ROUTE/MMT),
TS, Generic Data
In DSTP Payloads
From/To System Manager
(BXF)
To/From
Data Sources
(MDCoIP)
STL Link
IP/UDP/RTP
Microwave/Satellite/Fiber
≤ 1 Phy
Frame
Delay
(≤ 5secs)
ALP
Buffers
ALPs
LLS Ind.
Configuration
Mgr
STL
Payload
(STLTP)
EAS Trig.
Broadcast
Gateway
w/External
ALP Gen
Broadcast
Gateway
w/Internal
ALP Gen
IP
UDP
RTP
PLP Mux
PLPs
USB
Crypto
Token
Security
Device
Security
Data
Processor
Security
Data
Stream
P
Security
Keys
Figure 4.2 System architecture.
Bit Int’l
FEC Mapper LDM MIMO Time Int’l OFDM
Framer/
Preamble
Inserter
Freq Int’l Pilot/
Tone
Reserve
MISO IFFT PAPR GI
≤ 1sec
Network
Comp.
Buffers
PLPs PLPs PLPs PLPs PLPs PLPs PLPs PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
PLP Dem
SMPTE
ST 2022-1
ECC
Decoder
SMPTE
ST 2022-1
ECC
Encoder
Authentication STL Rcvr
STL Xmtr
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
IP
Packetizers
Baseband
Packetizers
PLPs
PLPs
Scheduler
Timing
& Mgt
Generator
Preamble
Generator
ALP
Demux
ALP
Mux
IP
UDP
RTP
ALPs
ALP
Encapsulation
ALPs
Data Source
Data Source
Data Source
Data Source
Scrambler
PLPs
ALP
Payload
(ALPTP)
STL
Payload
(STLTP)
IP (ROUTE/MMT),
TS, Generic Data
In DSTP Payloads
From/To System Manager
(BXF)
To/From
Data Sources
(MDCoIP)
STL Link
IP/UDP/RTP
Microwave/Satellite/Fiber
≤ 1 Phy
Frame
Delay
(≤ 5secs)
ALP
Buffers
ALPs
LLS Ind.
Configuration
Mgr
STL
Payload
(STLTP)
EAS Trig.
Broadcast
Gateway
w/External
ALP Gen
Broadcast
Gateway
w/Internal
ALP Gen
IP
UDP
RTP
PLP Mux
PLPs
USB
Crypto
Token
Security
Device
Security
Data
Processor
Security
Data
Stream
P
Security
Keys
Figure 4.2 System architecture.
Figure 4.2 shows a possible system architecture; other configurations are possib
Bit Int’l
FEC Mapper LDM MIMO Time Int’l OFDM
Framer/
Preamble
Inserter
Freq Int’l Pilot/
Tone
Reserve
MISO IFFT PAPR GI
≤ 1sec
Network
Comp.
Buffers
PLPs PLPs PLPs PLPs PLPs PLPs PLPs PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
PLP Dem
SMPTE
ST 2022-1
ECC
Decoder
SMPTE
ST 2022-1
ECC
Encoder
Authentication STL Rcvr
STL Xmtr
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
IP
Packetizers
Baseband
Packetizers
PLPs
PLPs
Scheduler
Timing
& Mgt
Generator
Preamble
Generator
ALP
Demux
ALP
Mux
IP
UDP
RTP
ALPs
ALP
Encapsulation
ALPs
Data Source
Data Source
Data Source
Data Source
Scrambler
PLPs
ALP
Payload
(ALPTP)
STL
Payload
(STLTP)
IP (ROUTE/MMT),
TS, Generic Data
In DSTP Payloads
From/To System Manager
(BXF)
To/From
Data Sources
(MDCoIP)
STL Link
IP/UDP/RTP
Microwave/Satellite/Fiber
≤ 1 Phy
Frame
Delay
(≤ 5secs)
ALP
Buffers
ALPs
LLS Ind.
Configuration
Mgr
STL
Payload
(STLTP)
EAS Trig.
Broadcast
Gateway
w/External
ALP Gen
Broadcast
Gateway
w/Internal
ALP Gen
IP
UDP
RTP
PLP Mux
PLPs
USB
Crypto
Token
Security
Device
Security
Data
Processor
Security
Data
Stream
P
Security
Keys
Figure 4.2 System architecture.
Figure 4.2 shows a possible system architecture; other configurations are possib
SM
ST 20
EC
Dec
SMPTE
ST 2022-1
ECC
Encoder
Authentication STL Rcvr
STL Xmtr
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
IP
Packetizers
Baseband
Packetizers
PLPs
PLPs
Scheduler
& Mgt
Generator
Preamble
Generator
ALP
Demux
ALP
Mux
IP
UDP
RTP
ALPs
ALP
Encapsulation
ALPs
Data Source
Data Source
Data Source
Data Source
ALP
Payload
(ALPTP)
STL
Payload
(STLTP)
IP (ROUTE/MMT),
TS, Generic Data
In DSTP Payloads
STL Link
IP/UDP/RTP
Microwave/Satellite/Fiber
≤ 1 Phy
Frame
Delay
(≤ 5secs)
ALP
Buffers
ALPs
LLS Ind.
EAS Trig.
IP
UDP
RTP
PLP Mux
PLPs
Device Data
Processor
Security
Data
Stream
Keys
Figure 4.2 System architecture.
Figure 4.2 shows a possible system architecture; other configurations are
considering system configurations, data rates and interfaces between functional
taken into account in developing practical implementations.
System Manager
Configuration aspects of the overall system are controlled by a single entity c
Manager, which is represented in Figure 4.2 only as a connection to the Configura
the Broadcast Gateway. A System Manager can be anything from a web-page bas
with manual data entry to a fully automated system; its scope is control of an ov
system. The System Manager provides high-level configuration parameters for nu
Bit Int’l
FEC Mapper LDM MIMO Time Int’l OFDM
Framer/
Preamble
Inserter
Freq Int’l Pilot/
Tone
Reserve
MISO IFFT PAPR
≤ 1sec
Network
Comp.
Buffers
Fr Fr Fr Fr Fr
ST
D
SMPTE
ST 2022-1
ECC
Encoder
Authentication STL Rcvr
STL Xmtr
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
IP
Packetizers
Baseband
Packetizers
PLPs
PLPs
Scheduler
Timing
& Mgt
Generator
Preamble
Generator
ALP
Demux
ALP
Mux
IP
UDP
RTP
ALPs
ALP
Encapsulation
ALPs
Data Source
Data Source
Data Source
Data Source
Scrambler
PLPs
ALP
Payload
(ALPTP)
STL
Payload
(STLTP)
IP (ROUTE/MMT),
TS, Generic Data
In DSTP Payloads
From/To System Manager
(BXF)
To/From
Data Sources
(MDCoIP)
STL Link
IP/UDP/RTP
Microwave/Satellite/Fiber
≤ 1 Phy
Frame
Delay
(≤ 5secs)
ALP
Buffers
ALPs
LLS Ind.
Configuration
Mgr
EAS Trig.
Broadcast
Gateway
w/External
ALP Gen
Broadcast
Gateway
w/Internal
ALP Gen
IP
UDP
RTP
PLP Mux
PLPs
USB
Crypto
Token
Security
Device
Security
Data
Processor
Security
Data
Stream
Keys
Figure 4.2 System architecture.
ATSC S32-266r33 Revision of A/324:2018, S
Bit Int’l
FEC Mapper LDM MIMO
≤ 1sec
Network
Comp.
Buffers
Preamble
Parser
PLPs PLPs PLPs PLPs
Timing
Manager
B
U
F
F
E
R
B
U
F
F
E
R
PLPs
GNSS Time
TAD
IP
Packetizer
Baseband
Packetizers
PLPs
Scheduler
Preamble
Generator
ALP
Demux
ALP
Mux
IP
UDP
RTP
ALPs
ALP
Encapsulation
ALPs
Data Source
Data Source
Data Source
Data Source
Scrambler
PLPs
ALP
Payload
(ALPTP)
IP (ROUTE/MMT),
TS, Generic Data
In DSTP Payloads
From/To System Manager
(BXF)
To/From
Data Sources
(MDCoIP)
≤ 1 Phy
Frame
Delay
(≤ 5secs)
ALP
Buffers
ALPs
LLS Ind.
Configuration
Mgr
EAS Trig.
Broadcast
Gateway
w/Internal
ALP Gen
IP
UDP
RTP
Figure 4.2
ALP
Mux
ALP
Encapsulation
ALPs
Data Source
Data Source
Data Source
Data Source
IP (ROUTE/MMT),
TS, Generic Data
In DSTP Payloads
From/To System Manager
(BXF)
To/From
Data Sources
(MDCoIP)
Broadcast
Gateway
w/Internal
ALP Gen
IP
UDP
RTP
Figure 4.2 sho
considering system
taken into account i
System Man
Configuration aspe
Manager, which is r
the Broadcast Gate
with manual data e
system. The System
functions. The Syst
chain. It controls th
configurations of t
sessions that suppo
SMPTE
ST 2022-1
ECC
Encoder
Authentication STL Xmtr
IP
UDP
RTP
IP
UDP
RTP
IP
Packetizers
Baseband
Packetizers
PLPs
PLPs
Scheduler
Timing
& Mgt
Generator
Preamble
Generator
ALP
Demux
ALP
Mux
IP
UDP
RTP
ALPs
ALP
Encapsulation
ALPs
Data Source
Data Source
Data Source
Data Source
ALP
Payload
(ALPTP)
STL
Payload
(STLTP)
IP (ROUTE/MMT),
TS, Generic Data
In DSTP Payloads
Data Sources
(MDCoIP)
STL Lin
IP/UDP/R
Microwave/Sate
≤ 1 Phy
Frame
Delay
(≤ 5secs)
ALP
Buffers
ALPs
LLS Ind.
EAS Trig.
IP
UDP
RTP
PLP Mux
PLPs
Token
Security
Device
Security
Data
Processor
Security
Data
Stream
Keys
Figure 4.2 System architecture.
Figure 4.2 shows a possible system architecture; other configur
considering system configurations, data rates and interfaces between
taken into account in developing practical implementations.
System Manager
Configuration aspects of the overall system are controlled by a sing
SMPTE
ST 2022-1
ECC
Encoder
Authentication STL Xmtr
IP
UDP
RTP
IP
UDP
RTP
IP
Packetizers
Baseband
Packetizers
PLPs
PLPs
Scheduler
Timing
& Mgt
Generator
Preamble
Generator
ALP
Demux
ALP
Mux
IP
UDP
RTP
ALPs
ALP
Encapsulation
ALPs
Data Source
Data Source
Data Source
Data Source
ALP
Payload
(ALPTP)
STL
Payload
(STLTP)
IP (ROUTE/MMT),
TS, Generic Data
In DSTP Payloads
Data Sources
(MDCoIP)
STL Link
IP/UDP/RTP
Microwave/Satellite/Fiber
≤ 1 Phy
Frame
Delay
(≤ 5secs)
ALP
Buffers
ALPs
LLS Ind.
EAS Trig.
IP
UDP
RTP
PLP Mux
PLPs
Token
Security
Device
Security
Data
Processor
Security
Data
Stream
Keys
Figure 4.2 System architecture.
Figure 4.2 shows a possible system architecture; other configuratio
considering system configurations, data rates and interfaces between fun
taken into account in developing practical implementations.
System Manager
Configuration aspects of the overall system are controlled by a single
ECC
Decoding
& STLTP
Demultiplexing
STL Rcvr
STL Xmtr
IP
UDP
RTP
IP
UDP
RTP
STLTP
Formatting
& ECC
Encoding
STL
Pre-Processor
PLPs
Configuration Mgr
/Scheduler
ALPTP
Receiver
ALPTP
Formatting
IP
UDP
RTP
ALPs
ALPTP STLTP
STL Link
IP/UDP/RTP
Microwave/Satellite/Fiber
Preamble Information
Timing & Mgt Information
STLTP
Coded
Modulation
Input
Formatting
Framing/
Structure
Waveform
Generation
Preamble
Parser
Buffer
Broadcast
Gateway
Figure 4.1 High-level overview of system configuration.
o-one correspondence between individual Streams of ALP packets and
prepare ALP packets for Transmission, in the Broadcast Gateway, the ALP
lated in Baseband Packets (BBPs), which have defined sizes that are
meter (Kpayload) related to the specific characteristics of the particular PLP(s)
e carried. The sizes of the BBPs in a given Stream are set to assure that the
the related PLP in a frame is filled by the BBPs derived from an associated
ALP packets either are segmented or are concatenated so that they fill the
e BBPs carrying them as completely as possible without overflowing the
ow of data through the system, several buffers are required to hold data for
ECC
Decoding
& STLTP
Demultiplexing
STL Rcvr
STL Xmtr
IP
UDP
RTP
IP
UDP
RTP
STLTP
Formatting
& ECC
Encoding
STL
Pre-Processor
PLPs
Configuration Mgr
/Scheduler
ALPTP
Receiver
ALPTP
Formatting
IP
UDP
RTP
ALPs
ALP
Generation
ALPs
Data Sources
ALPTP STLTP
STL Link
IP/UDP/RTP
Microwave/Satellite/Fiber
ATSC A/330 ALP &
A/331 Signaling, etc.
Transport Layer
System
Manager
Preamble Information
Timing & Mgt Information
STLTP
Coded
Modulation
Input
Formatting
Framing/
Structure
Waveform
Generation
Preamble
Parser
Buffer
Broadcast
Gateway
DSTP
Broadcast
Gateway
w/Internal
ALP Gen.
Figure 4.1 High-level overview of system configuration.
There is a one-to-one correspondence between individual Streams of ALP packets and
individual PLPs. To prepare ALP packets for Transmission, in the Broadcast Gateway, the ALP
packets are encapsulated in Baseband Packets (BBPs), which have defined sizes that are
determined by a parameter (Kpayload) related to the specific characteristics of the particular PLP(s)
in which they will be carried. The sizes of the BBPs in a given Stream are set to assure that the
assigned capacity of the related PLP in a frame is filled by the BBPs derived from an associated
ALP packet Stream. ALP packets either are segmented or are concatenated so that they fill the
allocated space in the BBPs carrying them as completely as possible without overflowing the
available space.
ECC
Decoding
& STLTP
Demultiplexing
STL Rcvr
STL Xmtr
IP
UDP
RTP
IP
UDP
RTP
STLTP
Formatting
& ECC
Encoding
STL
Pre-Processor
PLPs
Configuration Mgr
/Scheduler
ALPTP
Receiver
ALPTP
Formatting
IP
UDP
RTP
ALPs
ALP
Generation
ALPs
Data Sources
ALPTP STLTP
STL Link
IP/UDP/RTP
Microwave/Satellite/Fiber
ATSC A/330 ALP &
A/331 Signaling, etc.
Transport Layer
System
Manager
Preamble Information
Timing & Mgt Information
STLTP
Coded
Modulation
Input
Formatting
Framing/
Structure
Waveform
Generation
Parser
Buffer
Broadcast
Gateway
DSTP
Broadcast
Gateway
w/Internal
ALP Gen.
Figure 4.1 High-level overview of system configuration.
There is a one-to-one correspondence between individual Streams of ALP packets and
individual PLPs. To prepare ALP packets for Transmission, in the Broadcast Gateway, the ALP
packets are encapsulated in Baseband Packets (BBPs), which have defined sizes that are
determined by a parameter (Kpayload) related to the specific characteristics of the particular PLP(s)
in which they will be carried. The sizes of the BBPs in a given Stream are set to assure that the
assigned capacity of the related PLP in a frame is filled by the BBPs derived from an associated
ALP packet Stream. ALP packets either are segmented or are concatenated so that they fill the
allocated space in the BBPs carrying them as completely as possible without overflowing the
available space.
ECC
Decoding
& STLTP
Demultiplexing
STL Rcvr
STL Xmtr
IP
UDP
RTP
IP
UDP
RTP
STLTP
Formatting
& ECC
Encoding
STL
Pre-Processor
PLPs
Configuration Mgr
/Scheduler
ALPTP
Receiver
ALPTP
Formatting
IP
UDP
RTP
ALPs
s
ALPTP STLTP
STL Link
IP/UDP/RTP
Microwave/Satellite/Fiber
Preamble Information
Timing & Mgt Information
STLTP
Broadcast
Gateway
t
al
Figure 4.1 High-level overview of system configuration.
-to-one correspondence between individual Streams of ALP packets and
prepare ALP packets for Transmission, in the Broadcast Gateway, the ALP
ulated in Baseband Packets (BBPs), which have defined sizes that are
ameter (Kpayload) related to the specific characteristics of the particular PLP(s)
be carried. The sizes of the BBPs in a given Stream are set to assure that the
f the related PLP in a frame is filled by the BBPs derived from an associated
. ALP packets either are segmented or are concatenated so that they fill the
he BBPs carrying them as completely as possible without overflowing the
flow of data through the system, several buffers are required to hold data for
ignment of data emission. Buffering also is required in certain instances to
o be obtained from a data Stream and used to control particular functionality
e the corresponding data is processed further. Two specific instances of such
e system. The first buffer inserts at least one Physical Layer frame of delay in
ECC
Decoding
& STLTP
Demultiplexing
STL Rcvr
STL Xmtr
IP
UDP
RTP
IP
UDP
RTP
STLTP
Formatting
& ECC
Encoding
STL
Pre-Processor
PLPs
Configuration Mgr
/Scheduler
ALPTP
Receiver
TP
tting
IP
UDP
RTP
ALPs
ALPTP STLTP
STL Link
IP/UDP/RTP
Microwave/Satellite/Fiber
Preamble Information
Timing & Mgt Information
STLTP
Broadcast
Gateway
ure 4.1 High-level overview of system configuration.
one correspondence between individual Streams of ALP packets and
epare ALP packets for Transmission, in the Broadcast Gateway, the ALP
ed in Baseband Packets (BBPs), which have defined sizes that are
ter (Kpayload) related to the specific characteristics of the particular PLP(s)
arried. The sizes of the BBPs in a given Stream are set to assure that the
e related PLP in a frame is filled by the BBPs derived from an associated
LP packets either are segmented or are concatenated so that they fill the
BBPs carrying them as completely as possible without overflowing the
of data through the system, several buffers are required to hold data for
ment of data emission. Buffering also is required in certain instances to
e obtained from a data Stream and used to control particular functionality
e corresponding data is processed further. Two specific instances of such
ECC
Decoding
& STLTP
Demultiplexing
STL Rcvr
STL Xmtr
IP
UDP
RTP
IP
UDP
RTP
STLTP
Formatting
& ECC
Encoding
STL
Pre-Processor
PLPs
Configuration Mgr
/Scheduler
ALPTP
Receiver
ALPTP
Formatting
IP
UDP
RTP
ALPs
ALPTP STLTP
STL Link
IP/UDP/RTP
Microwave/Satellite/Fiber
Preamble Information
Timing & Mgt Information
STLTP
Broadcast
Gateway
t
l
Figure 4.1 High-level overview of system configuration.
-to-one correspondence between individual Streams of ALP packets and
prepare ALP packets for Transmission, in the Broadcast Gateway, the ALP
ulated in Baseband Packets (BBPs), which have defined sizes that are
ameter (Kpayload) related to the specific characteristics of the particular PLP(s)
e carried. The sizes of the BBPs in a given Stream are set to assure that the
the related PLP in a frame is filled by the BBPs derived from an associated
ALP packets either are segmented or are concatenated so that they fill the
he BBPs carrying them as completely as possible without overflowing the
low of data through the system, several buffers are required to hold data for
ignment of data emission. Buffering also is required in certain instances to
o be obtained from a data Stream and used to control particular functionality
e the corresponding data is processed further. Two specific instances of such
e system. The first buffer inserts at least one Physical Layer frame of delay in
sor to enable sending Preamble information for a given Physical Layer frame
ECC
Decoding
& STLTP
Demultiplexing
STL Rcvr
STL Xmtr
IP
UDP
RTP
IP
UDP
RTP
STLTP
Formatting
& ECC
Encoding
STL
Pre-Processor
PLPs
Configuration Mgr
/Scheduler
ALPTP
Receiver
TP
tting
IP
UDP
RTP
ALPs
ALPTP STLTP
STL Link
IP/UDP/RTP
Microwave/Satellite/Fiber
Preamble Information
Timing & Mgt Information
STLTP
Broadcast
Gateway
ure 4.1 High-level overview of system configuration.
one correspondence between individual Streams of ALP packets and
epare ALP packets for Transmission, in the Broadcast Gateway, the ALP
ed in Baseband Packets (BBPs), which have defined sizes that are
ter (Kpayload) related to the specific characteristics of the particular PLP(s)
arried. The sizes of the BBPs in a given Stream are set to assure that the
e related PLP in a frame is filled by the BBPs derived from an associated
LP packets either are segmented or are concatenated so that they fill the
BBPs carrying them as completely as possible without overflowing the
of data through the system, several buffers are required to hold data for
ment of data emission. Buffering also is required in certain instances to
e obtained from a data Stream and used to control particular functionality
e corresponding data is processed further. Two specific instances of such
stem. The first buffer inserts at least one Physical Layer frame of delay in
PLP Demux
SMPTE
ST 2022-1
ECC
Decoder
SMPTE
ST 2022-1
ECC
Encoder
Authentication STL Rcvr
STL Xmtr
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
IP
Packetizers
Baseband
Packetizers
PLPs
PLPs
Scheduler
Timing
& Mgt
Generator
Preamble
Generator
ALP
Demux
ALP
Mux
IP
UDP
RTP
ALPs
ALP
Encapsulation
ALPs
Data Source
Data Source
Data Source
Data Source
ALP
Payload
(ALPTP)
STL
Payload
(STLTP)
IP (ROUTE/MMT),
TS, Generic Data
In DSTP Payloads
o System Manager
(BXF)
To/From
Data Sources
(MDCoIP)
STL Link
IP/UDP/RTP
Microwave/Satellite/Fiber
≤ 1 Phy
Frame
Delay
(≤ 5secs)
ALP
Buffers
ALPs
LLS Ind.
Configuration
Mgr
STL
Payload
(STLTP)
EAS Trig.
Broadcast
Gateway
w/External
ALP Gen
Broadcast
Gateway
w/Internal
ALP Gen
IP
UDP
RTP
PLP Mux
PLPs
USB
Crypto
Token
Security
Device
Security
Data
Processor
Security
Data
Stream
PLPs
Authentication
USB
Crypto
Token
Security
Device
Security
Data
Processor
Keys
Security Data Stream
Keys
Figure 4.2 System architecture.
Figure 4.2 shows a possible system architecture; other configurations are possible. Wh
nsidering system configurations, data rates and interfaces between functional blocks must
ken into account in developing practical implementations.
System Manager
onfiguration aspects of the overall system are controlled by a single entity called a Syste
P
SMPTE
ST 2022-1
ECC
Decoder
SMPTE
ST 2022-1
ECC
Encoder
Authentication STL Rcvr
STL Xmtr
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
IP
Packetizers
Baseband
Packetizers
PLPs
PLPs
Scheduler
Timing
& Mgt
Generator
Preamble
Generator
ALP
Demux
ALP
Mux
IP
UDP
RTP
ALPs
ALP
Encapsulation
ALPs
Data Source
Data Source
Data Source
Data Source
ALP
Payload
(ALPTP)
STL
Payload
(STLTP)
IP (ROUTE/MMT),
TS, Generic Data
In DSTP Payloads
From/To System Manager
(BXF)
To/From
Data Sources
(MDCoIP)
STL Link
IP/UDP/RTP
Microwave/Satellite/Fiber
≤ 1 Phy
Frame
Delay
(≤ 5secs)
ALP
Buffers
ALPs
LLS Ind.
Configuration
Mgr
STL
Payload
(STLTP)
EAS Trig.
Broadcast
Gateway
w/External
ALP Gen
Broadcast
Gateway
w/Internal
ALP Gen
IP
UDP
RTP
PLP Mux
PLPs
USB
Crypto
Token
Security
Device
Security
Data
Processor
Security
Data
Stream
S
Keys
Figure 4.2 System architecture.
Figure 4.2 shows a possible system architecture; other configurations are poss
considering system configurations, data rates and interfaces between functional bloc
taken into account in developing practical implementations.
System Manager
Configuration aspects of the overall system are controlled by a single entity calle
PLP Demux
SMPTE
ST 2022-1
ECC
Decoder
SMPTE
ST 2022-1
ECC
Encoder
Authentication STL Rcvr
STL Xmtr
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
IP
Packetizers
Baseband
Packetizers
PLPs
PLPs
Scheduler
Timing
& Mgt
Generator
Preamble
Generator
ALP
Demux
ALP
Mux
IP
UDP
RTP
ALPs
ALP
Encapsulation
ALPs
Data Source
Data Source
Data Source
Data Source
ALP
Payload
(ALPTP)
STL
Payload
(STLTP)
IP (ROUTE/MMT),
TS, Generic Data
In DSTP Payloads
o System Manager
(BXF)
To/From
Data Sources
(MDCoIP)
STL Link
IP/UDP/RTP
Microwave/Satellite/Fiber
≤ 1 Phy
Frame
Delay
(≤ 5secs)
ALP
Buffers
ALPs
LLS Ind.
Configuration
Mgr
STL
Payload
(STLTP)
EAS Trig.
Broadcast
Gateway
w/External
ALP Gen
Broadcast
Gateway
w/Internal
ALP Gen
IP
UDP
RTP
PLP Mux
PLPs
USB
Crypto
Token
Security
Device
Security
Data
Processor
Security
Data
Stream
PLPs
Authentication
USB
Crypto
Token
Security
Device
Security
Data
Processor
Keys
Security Data Stream
Keys
Figure 4.2 System architecture.
Figure 4.2 shows a possible system architecture; other configurations are possible. Wh
nsidering system configurations, data rates and interfaces between functional blocks must
ken into account in developing practical implementations.
System Manager
PLP Demux
SMPTE
ST 2022-1
ECC
Decoder
SMPTE
ST 2022-1
ECC
Encoder
Authentication STL Rcvr
STL Xmtr
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
IP
Packetizers
Baseband
Packetizers
PLPs
PLPs
Scheduler
Timing
& Mgt
Generator
Preamble
Generator
ALP
Demux
ALP
Mux
IP
UDP
RTP
ALPs
ALP
Encapsulation
ALPs
Data Source
Data Source
Data Source
Data Source
ALP
Payload
(ALPTP)
STL
Payload
(STLTP)
IP (ROUTE/MMT),
TS, Generic Data
In DSTP Payloads
o System Manager
(BXF)
To/From
Data Sources
(MDCoIP)
STL Link
IP/UDP/RTP
Microwave/Satellite/Fiber
≤ 1 Phy
Frame
Delay
(≤ 5secs)
ALP
Buffers
ALPs
LLS Ind.
Configuration
Mgr
STL
Payload
(STLTP)
EAS Trig.
Broadcast
Gateway
w/External
ALP Gen
Broadcast
Gateway
w/Internal
ALP Gen
IP
UDP
RTP
PLP Mux
PLPs
USB
Crypto
Token
Security
Device
Security
Data
Processor
Security
Data
Stream
PLPs
Authentication
USB
Crypto
Token
Security
Device
Security
Data
Processor
Keys
Security Data Stream
Keys
Figure 4.2 System architecture.
Figure 4.2 shows a possible system architecture; other configurations are possible. Wh
nsidering system configurations, data rates and interfaces between functional blocks must
ken into account in developing practical implementations.
System Manager
onfiguration aspects of the overall system are controlled by a single entity called a Syste
PLP Demux
SMPTE
ST 2022-1
ECC
Decoder
SMPTE
ST 2022-1
ECC
Encoder
Authentication STL Rcvr
STL Xmtr
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
IP
Packetizers
Baseband
Packetizers
PLPs
PLPs
Scheduler
Timing
& Mgt
Generator
Preamble
Generator
ALP
Demux
ALP
Mux
IP
UDP
RTP
ALPs
ALP
Encapsulation
ALPs
Data Source
Data Source
Data Source
Data Source
ALP
Payload
(ALPTP)
STL
Payload
(STLTP)
IP (ROUTE/MMT),
TS, Generic Data
In DSTP Payloads
o System Manager
(BXF)
To/From
Data Sources
(MDCoIP)
STL Link
IP/UDP/RTP
Microwave/Satellite/Fiber
≤ 1 Phy
Frame
Delay
(≤ 5secs)
ALP
Buffers
ALPs
LLS Ind.
Configuration
Mgr
STL
Payload
(STLTP)
EAS Trig.
Broadcast
Gateway
w/External
ALP Gen
Broadcast
Gateway
w/Internal
ALP Gen
IP
UDP
RTP
PLP Mux
PLPs
USB
Crypto
Token
Security
Device
Security
Data
Processor
Security
Data
Stream
PLPs
Authentication
USB
Crypto
Token
Security
Device
Security
Data
Processor
Keys
Security Data Stream
Keys
Figure 4.2 System architecture.
Figure 4.2 shows a possible system architecture; other configurations are possible. Wh
nsidering system configurations, data rates and interfaces between functional blocks must
ken into account in developing practical implementations.
System Manager
onfiguration aspects of the overall system are controlled by a single entity called a Syste
PLP Demux
SMPTE
ST 2022-1
ECC
Decoder
SMPTE
ST 2022-1
ECC
Encoder
Authentication STL Rcvr
STL Xmtr
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
IP
Packetizers
Baseband
Packetizers
PLPs
PLPs
Scheduler
Timing
& Mgt
Generator
Preamble
Generator
ALP
Demux
ALP
Mux
IP
UDP
RTP
ALPs
ALP
Encapsulation
ALPs
Data Source
Data Source
Data Source
Data Source
ALP
Payload
(ALPTP)
STL
Payload
(STLTP)
IP (ROUTE/MMT),
TS, Generic Data
In DSTP Payloads
o System Manager
(BXF)
To/From
Data Sources
(MDCoIP)
STL Link
IP/UDP/RTP
Microwave/Satellite/Fiber
≤ 1 Phy
Frame
Delay
(≤ 5secs)
ALP
Buffers
ALPs
LLS Ind.
Configuration
Mgr
STL
Payload
(STLTP)
EAS Trig.
Broadcast
Gateway
w/External
ALP Gen
Broadcast
Gateway
w/Internal
ALP Gen
IP
UDP
RTP
PLP Mux
PLPs
USB
Crypto
Token
Security
Device
Security
Data
Processor
Security
Data
Stream
PLPs
Authentication
USB
Crypto
Token
Security
Device
Security
Data
Processor
Keys
Security Data Stream
Keys
Figure 4.2 System architecture.
Figure 4.2 shows a possible system architecture; other configurations are possible. Wh
nsidering system configurations, data rates and interfaces between functional blocks must
ken into account in developing practical implementations.
System Manager
PLP Demux
SMPTE
ST 2022-1
ECC
Decoder
SMPTE
ST 2022-1
ECC
Encoder
Authentication STL Rcvr
STL Xmtr
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
IP
Packetizers
Baseband
Packetizers
PLPs
PLPs
Scheduler
Timing
& Mgt
Generator
Preamble
Generator
ALP
Demux
ALP
Mux
IP
UDP
RTP
ALPs
ALP
Encapsulation
ALPs
Data Source
Data Source
Data Source
Data Source
ALP
Payload
(ALPTP)
STL
Payload
(STLTP)
IP (ROUTE/MMT),
TS, Generic Data
In DSTP Payloads
(BXF)
To/From
Data Sources
(MDCoIP)
STL Link
IP/UDP/RTP
Microwave/Satellite/Fiber
≤ 1 Phy
Frame
Delay
(≤ 5secs)
ALP
Buffers
ALPs
LLS Ind.
STL
Payload
(STLTP)
EAS Trig.
w/External
ALP Gen
w/Internal
ALP Gen
IP
UDP
RTP
PLP Mux
PLPs
USB
Crypto
Token
Security
Device
Security
Data
Processor
Security
Data
Stream
PLPs
Authenticatio
USB
Crypto
Token
Security
Device
Security
Data
Processor
Keys
Security Data Stream
Keys
Figure 4.2 System architecture.
Figure 4.2 shows a possible system architecture; other configurations are possible. W
nsidering system configurations, data rates and interfaces between functional blocks must
en into account in developing practical implementations.
System Manager
nfiguration aspects of the overall system are controlled by a single entity called a Sys
anager, which is represented in Figure 4.2 only as a connection to the Configuration Manage
PLP Demux
SMPTE
ST 2022-1
ECC
Decoder
SMPTE
ST 2022-1
ECC
Encoder
entication STL Rcvr
STL Xmtr
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
iming
& Mgt
enerator
STL
Payload
(STLTP)
STL Link
IP/UDP/RTP
Microwave/Satellite/Fiber
STL
Payload
(STLTP)
w/External
ALP Gen
PLP Mux
PLPs
USB
Crypto
Token
Security
Device
Security
Data
Processor
Security
Data
Stream
PLPs
Authentication
USB
Crypto
Token
Security
Device
Security
Data
Processor
Keys
Security Data Stream
Keys
ystem architecture.
hitecture; other configurations are possible. When
and interfaces between functional blocks must be
lementations.
are controlled by a single entity called a System
nly as a connection to the Configuration Manager in
an be anything from a web-page based setup screen
Korean Broadcasting System | Broadcast Technical Research Institute
Bit Int’l
FEC Mapper LDM MIMO Time Int’l OFDM
Framer/
Preamble
Inserter
Freq Int’l Pilot/
Tone
Reserve
MISO IFFT PAPR GI
≤ 1sec
Network
Comp.
Buffers
PLPs PLPs PLPs PLPs PLPs PLPs PLPs PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
SMPTE
ST 2022-1
ECC
Decoder
SMPTE
ST 2022-1
ECC
Encoder
Authentication STL Rcvr
STL Xmtr
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
IP
UD
RT
IP
Packetizers
Baseband
Packetizers
PLPs
PLPs
Scheduler
Timing
& Mgt
Generator
Preamble
Generator
ALP
Demux
ALP
Mux
IP
UDP
RTP
ALPs
ALP
Encapsulation
ALPs
Data Source
Data Source
Data Source
Data Source
Scrambler
PLPs
ALP
Payload
(ALPTP)
STL
Payload
(STLTP)
IP (ROUTE/MMT),
TS, Generic Data
In DSTP Payloads
From/To System Manager
(BXF)
To/From
Data Sources
(MDCoIP)
STL Link
IP/UDP/RTP
Microwave/Satellite/Fiber
≤ 1 Phy
Frame
Delay
(≤ 5secs)
ALP
Buffers
ALPs
LLS Ind.
Configuration
Mgr
ST
Paylo
(STL
EAS Trig.
Broadcast
Gateway
w/External
ALP Gen
Broadcast
Gateway
w/Internal
ALP Gen
IP
UDP
RTP
PLP Mux
PLPs
USB
Crypto
Token
Security
Device
Security
Data
Processor
Security
Data
Stream
Keys
Figure 4.2 System architecture.
Figure 4.2 shows a possible system architecture; other configurations are po
Bit Int’l
FEC Mapper LDM MIMO Time Int’l OFDM
Framer/
Preamble
Inserter
Freq Int’l Pilot/
Tone
Reserve
MISO IFFT
≤ 1sec
Network
Comp.
Buffers
Preamble
Parser
PLPs PLPs PLPs PLPs PLPs PLPs PLPs PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
SMPTE
ST 2022-1
ECC
Encoder
Authentication STL Xmtr
IP
UDP
RTP
IP
UDP
RTP
IP
Packetizers
Baseband
Packetizers
PLPs
PLPs
Scheduler
Timing
& Mgt
Generator
Preamble
Generator
ALP
Demux
ALP
Mux
IP
UDP
RTP
ALPs
ALP
Encapsulation
ALPs
Data Source
Data Source
Data Source
Data Source
Scrambler
PLPs
ALP
Payload
(ALPTP)
STL
Payload
(STLTP)
IP (ROUTE/MMT),
TS, Generic Data
In DSTP Payloads
From/To System Manager
(BXF)
To/From
Data Sources
(MDCoIP)
STL Link
IP/UDP/RTP
Microwave/Satellite/Fiber
≤ 1 Phy
Frame
Delay
(≤ 5secs)
ALP
Buffers
ALPs
LLS Ind.
Configuration
Mgr
EAS Trig.
Broadcast
Gateway
w/External
ALP Gen
Broadcast
Gateway
w/Internal
ALP Gen
IP
UDP
RTP
PLP Mux
PLPs
USB
Crypto
Token
Security
Device
Security
Data
Processor
Security
Data
Stream
Keys
Figure 4.2 System architecture.
Figure 4.2 shows a possible system architecture; other configuratio
Bit Int’l
FEC Mapper LDM MIMO Time Int’l OFDM
Framer/
Preamble
Inserter
Freq Int’l Pilot/
Tone
Reserve
MISO IFFT PAPR G
≤ 1sec
Network
Comp.
Buffers
Preamble
Parser
PLPs PLPs PLPs PLPs PLPs PLPs PLPs PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
SMPTE
ST 2022-1
ECC
Decoder
SMPTE
ST 2022-1
ECC
Encoder
Authentication STL Rcvr
STL Xmtr
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
U
R
IP
Packetizers
Baseband
Packetizers
PLPs
PLPs
Scheduler
Timing
& Mgt
Generator
Preamble
Generator
ALP
Demux
ALP
Mux
IP
UDP
RTP
ALPs
ALP
Encapsulation
ALPs
Data Source
Data Source
Data Source
Data Source
Scrambler
PLPs
ALP
Payload
(ALPTP)
STL
Payload
(STLTP)
IP (ROUTE/MMT),
TS, Generic Data
In DSTP Payloads
From/To System Manager
(BXF)
To/From
Data Sources
(MDCoIP)
STL Link
IP/UDP/RTP
Microwave/Satellite/Fiber
≤ 1 Phy
Frame
Delay
(≤ 5secs)
ALP
Buffers
ALPs
LLS Ind.
Configuration
Mgr
S
Pay
(ST
EAS Trig.
Broadcast
Gateway
w/External
ALP Gen
Broadcast
Gateway
w/Internal
ALP Gen
IP
UDP
RTP
PLP Mux
PLPs
USB
Crypto
Token
Security
Device
Security
Data
Processor
Security
Data
Stream
Keys
Figure 4.2 System architecture.
Bit Int’l
FEC Mapper LDM MIMO Time Int’l OFDM
Framer/
Preamble
Inserter
Freq Int’l Pilot/
Tone
Reserve
MISO IFFT PAPR G
≤ 1sec
Network
Comp.
Buffers
PLPs PLPs PLPs PLPs PLPs PLPs PLPs PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
SMPTE
ST 2022-1
ECC
Decoder
SMPTE
ST 2022-1
ECC
Encoder
Authentication STL Rcvr
STL Xmtr
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
U
R
IP
Packetizers
Baseband
Packetizers
PLPs
PLPs
Scheduler
Timing
& Mgt
Generator
Preamble
Generator
ALP
Demux
ALP
Mux
IP
UDP
RTP
ALPs
ALP
Encapsulation
ALPs
Data Source
Data Source
Data Source
Data Source
Scrambler
PLPs
ALP
Payload
(ALPTP)
STL
Payload
(STLTP)
IP (ROUTE/MMT),
TS, Generic Data
In DSTP Payloads
From/To System Manager
(BXF)
To/From
Data Sources
(MDCoIP)
STL Link
IP/UDP/RTP
Microwave/Satellite/Fiber
≤ 1 Phy
Frame
Delay
(≤ 5secs)
ALP
Buffers
ALPs
LLS Ind.
Configuration
Mgr
S
Pay
(ST
EAS Trig.
Broadcast
Gateway
w/External
ALP Gen
Broadcast
Gateway
w/Internal
ALP Gen
IP
UDP
RTP
PLP Mux
PLPs
USB
Crypto
Token
Security
Device
Security
Data
Processor
Security
Data
Stream
Keys
Figure 4.2 System architecture.
Figure 4.2 shows a possible system architecture; other configurations are po
Bit Int’l
FEC Mapper LDM MIMO Time Int’l OFDM
Framer/
Preamble
Inserter
Freq Int’l Pilot/
Tone
Reserve
MISO IFFT PAPR G
≤ 1sec
Network
Comp.
Buffers
PLPs PLPs PLPs PLPs PLPs PLPs PLPs PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
SMPTE
ST 2022-1
ECC
Decoder
SMPTE
ST 2022-1
ECC
Encoder
Authentication STL Rcvr
STL Xmtr
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
U
R
IP
Packetizers
Baseband
Packetizers
PLPs
PLPs
Scheduler
Timing
& Mgt
Generator
Preamble
Generator
ALP
Demux
ALP
Mux
IP
UDP
RTP
ALPs
ALP
Encapsulation
ALPs
Data Source
Data Source
Data Source
Data Source
Scrambler
PLPs
ALP
Payload
(ALPTP)
STL
Payload
(STLTP)
IP (ROUTE/MMT),
TS, Generic Data
In DSTP Payloads
From/To System Manager
(BXF)
To/From
Data Sources
(MDCoIP)
STL Link
IP/UDP/RTP
Microwave/Satellite/Fiber
≤ 1 Phy
Frame
Delay
(≤ 5secs)
ALP
Buffers
ALPs
LLS Ind.
Configuration
Mgr
S
Pay
(ST
EAS Trig.
Broadcast
Gateway
w/External
ALP Gen
Broadcast
Gateway
w/Internal
ALP Gen
IP
UDP
RTP
PLP Mux
PLPs
USB
Crypto
Token
Security
Device
Security
Data
Processor
Security
Data
Stream
Keys
Figure 4.2 System architecture.
Figure 4.2 shows a possible system architecture; other configurations are po
Korean Broadcasting System | Broadcast Technical Research Institute
Bit Int’l
FEC Mapper LDM MIMO Time Int’l OFDM
Framer/
Preamble
Inserter
Freq Int’l Pilot/
Tone
Reserve
MISO IFFT PAPR
≤ 1sec
Network
Comp.
Buffers
PLPs PLPs PLPs PLPs PLPs PLPs PLPs PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
SMPTE
ST 2022-1
ECC
Decoder
SMPTE
ST 2022-1
ECC
Encoder
Authentication STL Rcvr
STL Xmtr
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
IP
Packetizers
Baseband
Packetizers
PLPs
PLPs
Scheduler
Timing
& Mgt
Generator
Preamble
Generator
ALP
Demux
ALP
Mux
IP
UDP
RTP
ALPs
ALP
Encapsulation
ALPs
Data Source
Data Source
Data Source
Data Source
Scrambler
PLPs
ALP
Payload
(ALPTP)
STL
Payload
(STLTP)
IP (ROUTE/MMT),
TS, Generic Data
In DSTP Payloads
From/To System Manager
(BXF)
To/From
Data Sources
(MDCoIP)
STL Link
IP/UDP/RTP
Microwave/Satellite/Fiber
≤ 1 Phy
Frame
Delay
(≤ 5secs)
ALP
Buffers
ALPs
LLS Ind.
Configuration
Mgr
EAS Trig.
Broadcast
Gateway
w/External
ALP Gen
Broadcast
Gateway
w/Internal
ALP Gen
IP
UDP
RTP
PLP Mux
PLPs
USB
Crypto
Token
Security
Device
Security
Data
Processor
Security
Data
Stream
Keys
Figure 4.2 System architecture.
Figure 4.2 shows a possible system architecture; other configurations are p
Bit Int’l
FEC Mapper LDM MIMO Time Int’l OFDM
Framer/
Preamble
Inserter
Freq Int’l Pilot/
Tone
Reserve
MISO
≤ 1sec
Network
Comp.
Buffers
Preamble
Parser
PLPs PLPs PLPs PLPs PLPs PLPs PLPs PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
SMPTE
ST 2022-1
ECC
Encoder
Authentication STL Xmtr
IP
UDP
RTP
IP
UDP
RTP
IP
Packetizers
Baseband
Packetizers
PLPs
PLPs
Scheduler
Timing
& Mgt
Generator
Preamble
Generator
ALP
Demux
ALP
Mux
IP
UDP
RTP
ALPs
ALP
Encapsulation
ALPs
Data Source
Data Source
Data Source
Data Source
Scrambler
PLPs
ALP
Payload
(ALPTP)
STL
Payload
(STLTP)
IP (ROUTE/MMT),
TS, Generic Data
In DSTP Payloads
From/To System Manager
(BXF)
To/From
Data Sources
(MDCoIP)
STL Link
IP/UDP/RTP
Microwave/Satellite/Fib
≤ 1 Phy
Frame
Delay
(≤ 5secs)
ALP
Buffers
ALPs
LLS Ind.
Configuration
Mgr
EAS Trig.
Broadcast
Gateway
w/External
ALP Gen
Broadcast
Gateway
w/Internal
ALP Gen
IP
UDP
RTP
PLP Mux
PLPs
USB
Crypto
Token
Security
Device
Security
Data
Processor
Security
Data
Stream
Keys
Figure 4.2 System architecture.
Figure 4.2 shows a possible system architecture; other configurati
Bit Int’l
FEC Mapper LDM MIMO Time Int’l OFDM
Framer/
Preamble
Inserter
Freq Int’l Pilot/
Tone
Reserve
MISO IFFT PAPR
≤ 1sec
Network
Comp.
Buffers
Preamble
Parser
PLPs PLPs PLPs PLPs PLPs PLPs PLPs PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
SMPTE
ST 2022-
ECC
Decode
SMPTE
ST 2022-1
ECC
Encoder
Authentication STL Rcvr
STL Xmtr
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
IP
Packetizers
Baseband
Packetizers
PLPs
PLPs
Scheduler
Timing
& Mgt
Generator
Preamble
Generator
ALP
Demux
ALP
Mux
IP
UDP
RTP
ALPs
ALP
Encapsulation
ALPs
Data Source
Data Source
Data Source
Data Source
Scrambler
PLPs
ALP
Payload
(ALPTP)
STL
Payload
(STLTP)
IP (ROUTE/MMT),
TS, Generic Data
In DSTP Payloads
From/To System Manager
(BXF)
To/From
Data Sources
(MDCoIP)
STL Link
IP/UDP/RTP
Microwave/Satellite/Fiber
≤ 1 Phy
Frame
Delay
(≤ 5secs)
ALP
Buffers
ALPs
LLS Ind.
Configuration
Mgr
EAS Trig.
Broadcast
Gateway
w/External
ALP Gen
Broadcast
Gateway
w/Internal
ALP Gen
IP
UDP
RTP
PLP Mux
PLPs
USB
Crypto
Token
Security
Device
Security
Data
Processor
Security
Data
Stream
Keys
Figure 4.2 System architecture.
Bit Int’l
FEC Mapper LDM MIMO Time Int’l OFDM
Framer/
Preamble
Inserter
Freq Int’l Pilot/
Tone
Reserve
MISO IFFT PAPR
≤ 1sec
Network
Comp.
Buffers
PLPs PLPs PLPs PLPs PLPs PLPs PLPs PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
SMPTE
ST 2022-
ECC
Decode
SMPTE
ST 2022-1
ECC
Encoder
Authentication STL Rcvr
STL Xmtr
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
IP
Packetizers
Baseband
Packetizers
PLPs
PLPs
Scheduler
Timing
& Mgt
Generator
Preamble
Generator
ALP
Demux
ALP
Mux
IP
UDP
RTP
ALPs
ALP
Encapsulation
ALPs
Data Source
Data Source
Data Source
Data Source
Scrambler
PLPs
ALP
Payload
(ALPTP)
STL
Payload
(STLTP)
IP (ROUTE/MMT),
TS, Generic Data
In DSTP Payloads
From/To System Manager
(BXF)
To/From
Data Sources
(MDCoIP)
STL Link
IP/UDP/RTP
Microwave/Satellite/Fiber
≤ 1 Phy
Frame
Delay
(≤ 5secs)
ALP
Buffers
ALPs
LLS Ind.
Configuration
Mgr
EAS Trig.
Broadcast
Gateway
w/External
ALP Gen
Broadcast
Gateway
w/Internal
ALP Gen
IP
UDP
RTP
PLP Mux
PLPs
USB
Crypto
Token
Security
Device
Security
Data
Processor
Security
Data
Stream
Keys
Figure 4.2 System architecture.
Figure 4.2 shows a possible system architecture; other configurations are p
Bit Int’l
FEC Mapper LDM MIMO Time Int’l OFDM
Framer/
Preamble
Inserter
Freq Int’l Pilot/
Tone
Reserve
MISO IFFT PAPR
≤ 1sec
Network
Comp.
Buffers
PLPs PLPs PLPs PLPs PLPs PLPs PLPs PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
PHY
Fr
SMPTE
ST 2022-
ECC
Decode
SMPTE
ST 2022-1
ECC
Encoder
Authentication STL Rcvr
STL Xmtr
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
IP
Packetizers
Baseband
Packetizers
PLPs
PLPs
Scheduler
Timing
& Mgt
Generator
Preamble
Generator
ALP
Demux
ALP
Mux
IP
UDP
RTP
ALPs
ALP
Encapsulation
ALPs
Data Source
Data Source
Data Source
Data Source
Scrambler
PLPs
ALP
Payload
(ALPTP)
STL
Payload
(STLTP)
IP (ROUTE/MMT),
TS, Generic Data
In DSTP Payloads
From/To System Manager
(BXF)
To/From
Data Sources
(MDCoIP)
STL Link
IP/UDP/RTP
Microwave/Satellite/Fiber
≤ 1 Phy
Frame
Delay
(≤ 5secs)
ALP
Buffers
ALPs
LLS Ind.
Configuration
Mgr
EAS Trig.
Broadcast
Gateway
w/External
ALP Gen
Broadcast
Gateway
w/Internal
ALP Gen
IP
UDP
RTP
PLP Mux
PLPs
USB
Crypto
Token
Security
Device
Security
Data
Processor
Security
Data
Stream
Keys
Figure 4.2 System architecture.
Figure 4.2 shows a possible system architecture; other configurations are p
S
D
SMPTE
ST 2022-1
ECC
Encoder
Authentication STL Rcvr
STL Xmtr
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
IP
Packetizers
Baseband
Packetizers
PLPs
PLPs
Scheduler
Generator
ALP
Demux
ALP
Mux
IP
UDP
RTP
ALPs
ALP
Encapsulation
ALPs
Data Source
Data Source
Data Source
Data Source
ALP
Payload
(ALPTP)
STL
Payload
(STLTP)
IP (ROUTE/MMT),
TS, Generic Data
In DSTP Payloads
STL Link
IP/UDP/RTP
Microwave/Satellite/Fiber
≤ 1 Phy
Frame
Delay
(≤ 5secs)
ALP
Buffers
ALPs
EAS Trig.
IP
UDP
RTP
PLP Mux
PLPs
Processor
Security
Data
Stream
Keys
Figure 4.2 System architecture.
Figure 4.2 shows a possible system architecture; other configurations are
considering system configurations, data rates and interfaces between functiona
taken into account in developing practical implementations.
System Manager
Configuration aspects of the overall system are controlled by a single entity
Manager, which is represented in Figure 4.2 only as a connection to the Configur
the Broadcast Gateway. A System Manager can be anything from a web-page ba
with manual data entry to a fully automated system; its scope is control of an o
Bit Int’l
FEC Mapper LDM MIMO Time Int’l OFDM
Framer/
Preamble
Inserter
Freq Int’l Pilot/
Tone
Reserve
MISO IFFT PAPR
≤ 1sec
Network
Comp.
Buffers
Fr Fr Fr Fr Fr Fr
SMP
ST 20
EC
Deco
SMPTE
ST 2022-1
ECC
Encoder
Authentication STL Rcvr
STL Xmtr
IP
UDP
RTP
IP
UDP
RTP
IP
UDP
RTP
IP
Packetizers
Baseband
Packetizers
PLPs
PLPs
Scheduler
Timing
& Mgt
Generator
Preamble
Generator
ALP
Demux
ALP
Mux
IP
UDP
RTP
ALPs
ALP
Encapsulation
ALPs
Data Source
Data Source
Data Source
Data Source
Scrambler
ALP
Payload
(ALPTP)
STL
Payload
(STLTP)
IP (ROUTE/MMT),
TS, Generic Data
In DSTP Payloads
From/To System Manager
(BXF)
To/From
Data Sources
(MDCoIP)
STL Link
IP/UDP/RTP
Microwave/Satellite/Fiber
≤ 1 Phy
Frame
Delay
(≤ 5secs)
ALP
Buffers
ALPs
LLS Ind.
Configuration
Mgr
EAS Trig.
Broadcast
Gateway
w/External
ALP Gen
Broadcast
Gateway
w/Internal
ALP Gen
IP
UDP
RTP
PLP Mux
PLPs
USB
Crypto
Token
Security
Device
Security
Data
Processor
Security
Data
Stream
Keys
Figure 4.2 System architecture.
ATSC 3.0 Gateway
SMPTE 2022-1 FEC 적용 예시
(L,D)=(8,5)
전송률 증가율
= = 32.5%
8+5
40
5004
5002
239.255.9.30:5000
BGW
Setting
(STL)