RISC-V Open-Source Hardware Report “FPGA Development Diary” Author : @msyksphinz_dev 2017/12/18 RISC-V Day Tokyo 2017 http://msyksphinz.hatenablog.com

Introduction of open-source RISC-V hardware for RISC-V beginner • Some RISC-V open-source core are released from UCB, and available at GitHub. • RISC-V open-source design is better for first trial and evaluation of RISC-V • UCB design is best, because design is following latest RISC-V specification. • Introducing RISC-V open-source hardware Interested in RISC-V? What do you want to do with RISC-V? Do you have FPGA? No Today is RISC-V Day! Yes Connecting Accelerator and optimizing your application Studying RISC-V instruction set and trying to evaluate your application ZedBoard Application development in HiFive1 Evaluate Rocket-Chip on FPGA Rocket Chip RTL Simulation Start

For semiconductor industry, RISC-V open- source hardware is a good opportunity • Only Giant company follows latest technology • IP, EDA, wefar cost, package cost … • Small company can’t follow latest technology, even though they have good idea • They want to concentrate their valuable part in their chip. • Other parts(MCU, External I/O), they want to cut cost • Minimizing implementation cost of CPU “center of Chp” • To concentrate “most valuable parts” in a chip, it is important to cut “common parts”, as CPU • “RISC-V” can reduce cost • Free • Performance is not in the least inferior to other “commercial” CPU • Software ecosystem is growing, ready to use. is one of best choice to solve problem

All of RISC-V is open on GitHub • Compilers / Operating Systems • RISC-V support is merged into mainstream at GCC 7.1 • RISC-V support of LLVM/Clang is in progress by lowRISC project. • Linux Kernel 4.15 is already imported for RISC-V • Supporting RISC-V by many Linux distributions are in progress • SiFive’s U54-MC (64bit multi-core RISC-V SoC) supports Linux • Not only Linux, but also FreeBSD are supporting RISC-V • Many Programming Languages are supporting “RISC-V” architecture • Including “not official” project… • C/C++, Go, Rust, Ocaml, Java, Pascal… • GNU library (Glibc, Newlib, etc …) are already imported into RISC-V • ※ Presenter have tried to import “MicroPython” into RISC-V HiFive1 Board • Confirmed it works on ISS “Spike”. Detail is explained at https://riscv.org/software-status

RISC-V software environment • Instruction Set Simulator / Emulator • UCB Official Spike Simulator / Gem5 • QEMU • Angel (JavaScript RISC-V simulator!) • RISCVEMU : QEMU creator made fast RISC-V specialized simulator! • Freedom Studio by “SiFive” • Based on Eclipse • Linux, Mac, Windows platform support • RISC-V Board “HiFive1” • support Arduino IDE • C/C++ program can be also run on HiFive1 • Freedom-E-SDK • CUI compile environment using SDK can be constructed. • Supports HiFive, Freedom SoC PlatForm freedom-e-sdk bsp openocd riscv-gnu-toolchain software demo_gpio dhrystone welcome local_interrupt led_fade

Open source RISC-V core : Rocket-Core, BOOM SoC environment: Rocket-Chip, Freedom SoC • RISC-V Implementation developed by UCB • Single Issue 5-stage pipeline “Rocket-Core” • 2-way/4-way out-of-order core “BOOMv1”, “BOOMv2” • Rocket-Core, BOOM simulation environment “Rocket-Chip Generator” • Can be embed “Rocket-Core” or “BOOM”, and run RTL simulation, evaluate on FPGA. • Freedom SoC Environment developed by “SiFive” • Some of implementations can be downloaded from GitHub. • Rich peripherals support, compared with Rocket-Chip Generator Free Open Following the latest ISA spec Active development Rocket-Chip Generator Rocket-Core BOOMv1 BOOMv2 Freedom SoC E31 Core Complex E51 Core Complex U54-MC Core Complex Written in Chisel

Hardware description language “Chisel” • Hardware description languade based on Scala • Almost of RocketChip is written in Chisel • Finally Chisel designs are converted into Verilog. • Impl. and Spec. can be match, using Chisel • Converting Chisel→FIRRTL(IR) and, can generate other languages like VHDL. • Fast verification • Test pattern in Chisel(≒Scala) can run faster than Verilog. FIRRTL FPGA Verilog C++ Simulator FIRRTL ASIC Verilog

Rocket-Chip Generator, Freedom SoCの構成方法 • High Portability • Easy to configurate Rocket-Chip environment using Chisel • Supports many environments like Xilinx ZYNQ FPGA, Arty, Virtex Ultrascale Xilinx ARTY FPGA E300 Freedom SoC E3 Coreplex RV32E/IMACN ROM Debug AON UART SPIFlash SPI GPIO PWM I2C I-Cache 4kB D-Cache 16kB Custom Coprocessor Xilinx ZYNQ FPGA Rocket-Chip Generator RV64GC ROM Debug I-Cache 4kB D-Cache 16kB Custom Coprocessor AXI2TileLink ARM DRAM I/O class DefaultConfig extends Config( new WithNBigCores(1) ++ new BaseConfig) class TinyConfig extends Config( new WithNMemoryChannels(0) ++ new WithIncoherentTiles ++ new With1TinyCore ++ new BaseConfig) Easy to change Rocket’s configuration by Chisel

Easy create original RISC-V cores with Chisel VM Support class WithNBigCores(n: Int) extends Config((site, here, up) => { case RocketTilesKey => { val big = RocketTileParams( core = RocketCoreParams(mulDiv = Some(MulDivParams( mulUnroll = 8, mulEarlyOut = true, divEarlyOut = true))), dcache = Some(DCacheParams( rowBits = site(SystemBusKey).beatBits, nMSHRs = 0, blockBytes = site(CacheBlockBytes))), icache = Some(ICacheParams( ... } }) class With1TinyCore extends Config((site, here, up) => { case XLen => 32 case RocketTilesKey => List(RocketTileParams( core = RocketCoreParams( useVM = false, fpu = None, mulDiv = Some(MulDivParams(mulUnroll = 8))), btb = None, dcache = Some(DCacheParams( rowBits = site(SystemBusKey).beatBits, nSets = 256, // 16Kb scratchpad nWays = 1, nTLBEntries = 4, nMSHRs = 0, blockBytes = site(CacheBlockBytes), scratch = Some(0x80000000L))), … blockBytes = site(CacheBlockBytes))))) }) class TinyConfig extends Config( new WithNMemoryChannels(0) ++ new WithIncoherentTiles ++ new With1TinyCore ++ new BaseConfig) Parts of cores can be attached easily by Chisel. Base Configuration + Extensions – Unused modules. Main Pipeline FPU DIV I-cache config D-cache config I/F

FPGA Execution Environment • Synthesis for ZedBoard FPGA  Implementation • Convenient to use UCB’s fpga-zynq repos • https://github.com/ucb-bar/fpga-zynq • MIDAS project is better to run RTL simulation on FPGA? • (https://github.com/ucb-bar/midas-top-release) • Very simple steps to generate FPGA design • cd zedboard; make • FPGA bin file (.bin) • Files need to boot like FSBL, U-Boot, BOOT.bin • Peta-Linux build running on PS Part(ARM) • Build Linux running on RISC-V • Build environment automatically! • It is a waste to use this framework only with RISC-V. • The only step is copying built files in directory into SD card to boot FPGA. fpga-zynq rocket-chip zedboard zynq zc706 sub-repo Sythesis Directory Sythesis Directory Sythesis Directory

Rocket-Chip Generator RTL Simulation / FPGA Integration • RTL simulation environment • supports VCS/Verilator • Convert Chsiel design into Verilog, and running simulation. • Sythesis for FPGA, ASIC • Need to take care to replace SRAM • ASIC : emulator/generated-src/*.behav_srams.v for SRAM. • FPGA : Need to replace Behavior SRAM into BlockRAM correctly. • FIRRTL can extract array structure and separate, or embed into output Verilog file. Verilog FPGA Design RTL Simulation Rocket-Chip RTL simulation 0 10000 20000 30000 40000 50000 0 20000 40000 60000 80000 100000 120000 140000 Rocket Default Rocket Small Freedom-E300 BOOM v1 BOOM v2 RISC-V Design 合成結果 Vivadov.2016.2 ZYNQ 7z020-clg484 Total LUT FF

RISC-V’s Accelerator Interface • RoCC (Rocket Custom Coprocessor) • Direct connection with Rocket Core (L1DC, External MemoryIF) • RISC-V ISA’s custom instructions can control RoCC. CMD RESP RESP CMD Rocket Core L1 D-cache Accelerator CMD RESP External Original instruction can be create to customize the design. custom0 rd, rs1, rs2 ・rd, rs1, rs2’s register address information ・rs1, rs2 ‘s register data ・Instruction’s decode information

Example of Rocket-Chip’s customization: Create integer Dot Product Accelerator and connect Rocket Core Specify head address of two matrix and their length, fetch data automatically and multiply each of them and accumulate. 2-way SIMD can support because matrix type is int32_t, and RoCC I/F is 64-bit. × = 2-way SIMD: calculate 2-elem All implementation is open at: https://github.com/msyksphinz/rocket-chip/tree/feature/matrix32 Spped-up by overwrapping memory’s fetch and each calculation CMD RESP RESP CMD Rocket Core L1 D-cache Accelerator CMD RESP External H_addr MAD V_addr Written in Chisel

Example of Rocket-Chip’s customization: Performance evaluation  Running on ZedBoard  SW: Software Execution  HW1: Hardware Execution  Element calculate direction : Row  Column  HW2: Hardware Execution  Element calculate direction : Column  Row  8-times performance improvement by increasing matrix size 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 2 x 2 x 2 4 x 4 x 4 8 x 8 x 8 16 x16 x16 18 x24 x28 性能比率 Matrix size Performance improve rate: software execution time is 1.0. SW/SW HW1/SW HW2/SW SW HW1 HW2 2 x 2 x 2 233 119 139 4 x 4 x 4 1094 325 310 8 x 8 x 8 7299 1287 1296 16 x16 x16 58610 8258 7122 18 x24 x28 172256 19581 19565 SW/SW HW1/SW HW2/SW 2 x 2 x 2 1.0 1.958 1.676 4 x 4 x 4 1.0 3.366 3.529 8 x 8 x 8 1.0 5.671 5.632 16 x16 x16 1.0 7.097 8.229 18 x24 x28 1.0 8.797 8.804 Hardware performance improvement rate: software is 1.0. Performance of Matrix product using Dot Product Accelerator 8-times performance improvement by accelerator

Summary: RISC-V open source design helps the weak • Trying RISC-V by open-source implementation • No cost is needed to RISC-V evaluation • RISC-V Hardware/Software support is progressing steadily. • There are many ways to evaluate RISC-V • FPGA Board : Aggressive optimization by custom RISC-V core. • Evaluation Board : Easy to evaluate RISC-V application • Let’s looking at RISC-V materials! • https://riscv.org/specifications/ (RISC-V’s specification) • https://www.sifive.com (SiFive WebSite) • https://github.com/freechipsproject/rocket-chip (Rocket Chip) • https://github.com/sifive/freedom-e-sdk (Freedom SDK) • http://msyksphinz.hatenablog.com (Presenter's blog)