16.09.25 Chisel+FIRRTL/自作HDLの試作

by muojp

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ChiselͱFIRRTLͷ͔ͨΘΕ࣌ @muo_jp(ͳ͔͟Θ ͚͍) 2016/09/25, RTLΛޠΔձ(12)

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@muo_jp ιϑτ΢ΣΞാ (C#, Java, Python, TypeScriptํ໘) εϚʔτϑΥϯ޲͚ΞϓϦ WebαʔϏε C#޷͖

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ߴҐ߹੒͕੝Γ্͕ͬͯ ͍Δࡢࠓ

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ιϑτ΢ΣΞ։ൃऀ΋ߴҐ߹੒͋Ε͹ ϋʔυ͍͚ΔΜ͡Όͳ͍ͷͱ͍͏෩ை

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ߴҐ߹੒ܥͪΐͬͱ… ϕϯμʔʹϩοΫΠϯ͞Εͨ͘ͳ͍ ※Vivado HLSͰॻ͍ͯAͷੴʹͿͪࠐΉͱ͔ͪΐͬͱ SystemC΋OpenCL΋νϥݟͯ͠řƂŖͱͳͬͨ ํݴΛؤுֶͬͯͿKIAI͕଍Γͳ͔ͬͨ ͑ͬɺA++!?!? ֤छϕϯμʔඇґଘߴҐ߹੒ܥ(Synthesijer, PyCoRAM, Polyphony, Synverll, IROHAํ໘)͸ԕר͖ʹோΊͯ·͢

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݁Ռ

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ਖ਼߈๏ͰHDLΛษڧ RTLํ໘ͷํʹ͸ৗ͚ࣝͩͲ ιϑτ΢ΣΞॻ͍͍ͯͯ΋஌ Βͳ͍ॾʑΛֶΜͰελʔτ ஍఺·Ͱདྷͨ ϝλεςʔϒϧݱ৅ άϨΠίʔυ VHDL΋ා͘ͳ͘ͳͬͨ HDLʹΑΔߴੑೳσΟδλϧճ࿏ઃܭ  ʢ৿Ԭ ੅෉ ஶɺ2007೥2݄ ୈ4൛/  2012೥7݄ ిࢠ൛ ॳ൛ൃചɺCQग़൛ࣾʣ

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Chisel https://chisel.eecs.berkeley.edu/ UC Berkeleyͷݚڀάϧʔϓ࡞ (2012-) ScalaͰRTLهड़ ࣮ࡍͷར༻ྫ RISC-V࣮૷ͷRocket Chip

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Chisel (Chisel 2)ͷߏ଄ Chiselຊମ(֤छܕఆٛΛఏڙ) RTLίʔυ (ChiselྲّྀͷScala) ςετίʔυ (Scala) ίʔσΟϯάϑΣʔζ

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Chisel (Chisel 2)ͷߏ଄ ChiselϥϯλΠϜ RTLίʔυ (ChiselྲّྀͷScala) ςετίʔυ (Scala) ࣮ߦϑΣʔζ .vϑΝΠϧ .cppϑΝΠϧˠωΠςΟϒόΠφϦ ϑΝΠϧੜ੒ cycle-accurateͳςετ

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Chisel≠ߴҐ߹੒ܥ

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Chisel͸... εςʔτϚγϯͷࣗಈίϯύΠϧͳͲͯ͘͠Εͳ͍ ίʔυ͸ScalaͰॻ͕͘ɺ͋͘·Ͱ΋ճ࿏ੜ੒ίʔυ Λলྗهड़͢Δ΋ͷ

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Chiselͷྑ͍ͱ͜Ζ IntelliJ IDEAͷࢧԉΛϑϧʹड͚ͭͭRTLίʔυΛॻ͚Δ γϯϘϧ໊ͷޡΓɺԋࢉʹ͓͚ΔܕෆҰகΛ͖ͬͪΓ ϦΞϧλΠϜͰԡ͑ͯ͘͞ΕΔɻϦϑΝΫλ΋ڧ͍ ௨ৗͷScalaίʔυͰγϛϡϨʔγϣϯ݁ՌΛݕূͰ͖Δ ग़ྗ͕Verilog HDLͳͷͰ͋ͪͪ͜΁࣋ͪग़͠΍͍͢ macOS/Windows/Linux্Ͱॻ͚Δ (େࣄ!)

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ChiselͰॻ͍ͯMAX10΁

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Chiselίʔυྫ(TMDSม׵ ൈਮ)

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Simݕূίʔυ

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Simݕূίʔυ

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ScalaͬΆ͘ͳ͍͚ͲScalaͩ

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ଞͷAlt-HDL(ࢀߟ) SFL(Structured Function description Language) ࢀߟ: https://ja.wikipedia.org/wiki/SFL Spinal HDL http://spinalhdl.github.io/SpinalDoc/ ChiselʹΩϨͨਓ͕࡞Γ࢝ΊͨΠϯεύΠΞܥ ϚϧνΫϩοΫαϙʔτڧ͍ɺεςʔτϚγϯهड़ࢧԉ͋Γ (ࣗಈతʹ੾ͬͯ͘ΕΔΘ͚Ͱ͸ͳ͍)

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HDLੜ੒؀ڥʹ๬Ή΋ͷ ϚϧνϓϥοτϑΥʔϜαϙʔτ(macOS/Windows) ࣗ༝Ͱ྿Ձʹ࢖͑ͯࣗ༝ʹࣺͯΒΕΔ ϩοΫΠϯ, ϊʔαϯΩϡʔ. ΤσΟλαϙʔτ͕ڧ͍ ϗετݴޠͰςετΛॻ͍ͯγϛϡϨʔγϣϯݕূ

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Chisel 2 → Chisel 3

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Chisel 3ͷ ίʔσΟϯάϑΣʔζ Chiselຊମ(֤छܕఆٛΛఏڙ) RTLίʔυ (ChiselྲّྀͷScala) ςετίʔυ (Scala)

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ωΠςΟϒόΠφϦ Chisel 3ͷ࣮ߦϑΣʔζ ChiselϥϯλΠϜ RTLίʔυ (ChiselྲّྀͷScala) ςετίʔυ (Scala) FIRRTL Verilator .ﬁr .v cycle-accurateͳςετ

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FIRRTL(ݴޠɾπʔϧڞ༻໊)

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FIRRTLͷݴޠ࢓༷ https://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/ EECS-2016-9.pdf 50ϖʔδগʑ ·͋·͋෼͔Γ΍͍͢

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FIRRTLΛखॻ͖ͯ͠ΈΔ circuit Top : module HalfAdder : input clk : Clock input reset : UInt<1> input io_a : UInt<1> input io_b : UInt<1> output io_s : UInt<1> output io_c : UInt<1> skip io_s <= xor(io_a, io_b) io_c <= and(io_a, io_b) module Top : input clk : Clock input reset : UInt<1> inst halfAdder of HalfAdder halfAdder.io_a is invalid halfAdder.io_b is invalid halfAdder.clk <= clk halfAdder.reset <= reset

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FIRRTLΛखॻ͖ͯ͠Έͨ circuit͸ඞਢɺTop Level Module΋ඞਢ ػցతʹίʔυੜ੒͠΍ͦ͢͏ͳงғؾ͸͋Δ rocket.ﬁrΛಡΜͰΈΔͱɺϗετͱͷσόοά༻௨৴ͳͲΛຒΊͯΔ ৴߸Λ֎΁ग़ͯ͠σόοά͠΍͘͢͢Δͷ͸FIRRTLੜ੒ଆͷ੹೚? Chiselͷଞݴޠ൛Λ࡞࣮ͬͯ༻ΤϦΞ·Ͱ͍࣋ͬͯ͘ͷ͕໘౗ͦ͏ ͤΊͯඪ४ͷDUT௨৴ํ๏ΛܾΊ͓͍ͯͯ΄͍͠

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ͦΕ͸ͦ͏ͱ

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C#͕޷͖ (※ຊ୊)

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FIRRTLͷͬ͘͟Γ࢓༷ ϑϧ൛ͱαϒηοτ൛(LoFIRRTL) ग़ྗλʔήοτ͸ओʹVerilog HDL ੜ੒ͨ͠Verilog HDLίʔυΛVerilator΁৯ΘͤͯC++ ΁ม׵͢Δ

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FIRRTLͷC#ϑϩϯτΤϯυ Λ࡞ͬͨ

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class HalfAdder : Module { public HalfAdder() { var io = new { a = new UInt(isOut: false), b = new UInt(isOut: false), s = new UInt(isOut: true), c = new UInt(isOut: true) }; this.io = io; io.s.Assign(io.a + io.b); io.c.Assign(io.a ^ io.b); } } public class AdderGenerator { public static void Main() { FirrtlSharp.Generator.GenerateHDL(new HalfAdder()); } }

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... module HalfAdder( input clk, input reset, input io_a, input io_b, output io_s, output io_c ); assign io_s = io_a & io_b; assign io_c = io_a ^ io_b; endmodule module TopHalfAdder( input clk, input reset ); wire halfadder_clk; wire halfadder_reset; ...

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DEMO

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FIRRTL ྑ͍ͱ͜Ζ ΍͸ΓػցతʹίʔυΛੜ੒͠΍͍͢ (High)FIRRTL→LoFIRRTLͷม׵εςοϓΛࠁΜͰ͍͚ Δ Verilog HDLΛੜ੒ͯ࢝͠ΊͯΤϥʔు͘ Ͱ͸ͳ͍ sourcemapͷ࢓૊ΈΛ͍࣋ͬͯΔ

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FIRRTL ඍົͳͱ͜Ζ daemonϞʔυ͕ͳ͍ ϓϩηεىಈׂ͕ͱॏ͍ͷͰຖճىಈ͸ͨ͘͠ͳ͍ ϦΞϧλΠϜʹ͍ۙΤϥʔใࠂΛग़͍ͨ͠৔߹͸ঘߋ ϓϩηεؒ࿈ܞ͕͕ͬͭΓςΩετ? FIRRTLͷग़ྗΛparse͢Δͷ͸ෆໟ protobufͱ͔ɺͤΊͯJSONͰσʔλ࿈ܞͰ͖ͯ΄͍͠(ଟ෼ௐ΂͖ Εͯͳ͍͚ͩͰԿ͔͋Δ)

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FIRRTL#ࢼ࡞൛ ྑ͍ͱ͜Ζ ֤ioϙʔτͷೖྗΛΤσΟλͰָʹิ׬Ͱ͖Δ ͦΕͳΓʹ؆ܿͳه๏ͰVerilog HDLΛੜ੒Ͱ͖Δ ஍ຯʹsourcemapαϙʔτͨ͠ ʮVerilog HDLม׵͕ίέͯΔ͜ͷίʔυɺ  ɹC#ίʔυ֘౰Օॴ͸ͩ͜͜Αʯػೳ

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FIRRTL#ࢼ࡞൛ ࢒೦ͳͱ͜Ζ

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(C#ͷ)syntaxతͳࣄ৘ C#͸ϝιουݺͼग़͠΍incr/decrݺͼग़͠ͳͲΛߦ Θͳ͍ࣜͷΈͰจΛߏ੒ͤͯ͘͞Εͳ͍ io.s <= io.a + io.b;  ͱ͍͏ه๏͸<=ͷԋࢉࢠΦʔόʔϩʔυͰ͸ϜϦ ݁Ռɺio.s.Assign(...)ͱ͍͏൵͍͠ײ͡ʹͳͬͨ

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ࢼ࡞൛ͷ࣮૷໘(ࢼ࡞ͳͷͰ...) ࢒೦͕ൽΛඃͬͯΪϦΪϦಈ͍ͯΔ͙Β͍࢒೦ͷմ ςετػೳ΋౰વະ࣮૷ͩ͠ ΰϦԡ͠ίʔυͷҰ෦Λ͝ཡ͍ͩ͘͞ UIntҎ֎ͷܕΛ׬શແࢹ ioҎ֎ͷreg/wireΛແࢹ ৚݅෼ذΛແࢹ