16.09.25 Chisel+FIRRTL/自作HDLの試作

RTLを語る会(12)で発表した、ChiselとFIRRTL、そしてFIRRTLベースの自作HDLを試作した話です。

Transcript

1. ChiselͱFIRRTLͷ͔ͨΘΕ࣌ @muo_jp(ͳ͔͟Θ ͚͍) 2016/09/25, RTLΛޠΔձ(12)
2. @muo_jp ιϑτ΢ΣΞാ (C#, Java, Python, TypeScriptํ໘) εϚʔτϑΥϯ޲͚ΞϓϦ WebαʔϏε C#޷͖
3. ߴҐ߹੒͕੝Γ্͕ͬͯ ͍Δࡢࠓ
4. ιϑτ΢ΣΞ։ൃऀ΋ߴҐ߹੒͋Ε͹ ϋʔυ͍͚ΔΜ͡Όͳ͍ͷͱ͍͏෩ை
5. ߴҐ߹੒ܥͪΐͬͱ… ϕϯμʔʹϩοΫΠϯ͞Εͨ͘ͳ͍ ※Vivado HLSͰॻ͍ͯAͷੴʹͿͪࠐΉͱ͔ͪΐͬͱ SystemC΋OpenCL΋νϥݟͯ͠řƂŖͱͳͬͨ ํݴΛؤுֶͬͯͿKIAI͕଍Γͳ͔ͬͨ ͑ͬɺA++!?!? ֤छϕϯμʔඇґଘߴҐ߹੒ܥ(Synthesijer, PyCoRAM, Polyphony, Synverll, IROHAํ໘)͸ԕר͖ʹோΊͯ·͢
6. ݁Ռ
7. ਖ਼߈๏ͰHDLΛษڧ RTLํ໘ͷํʹ͸ৗ͚ࣝͩͲ ιϑτ΢ΣΞॻ͍͍ͯͯ΋஌ Βͳ͍ॾʑΛֶΜͰελʔτ ஍఺·Ͱདྷͨ ϝλεςʔϒϧݱ৅ άϨΠίʔυ VHDL΋ා͘ͳ͘ͳͬͨ HDLʹΑΔߴੑೳσΟδλϧճ࿏ઃܭ
 ʢ৿Ԭ ੅෉ ஶɺ2007೥2݄ ୈ4൛/
 2012೥7݄ ిࢠ൛ ॳ൛ൃചɺCQग़൛ࣾʣ
8. Chisel https://chisel.eecs.berkeley.edu/ UC Berkeleyͷݚڀάϧʔϓ࡞ (2012-) ScalaͰRTLهड़ ࣮ࡍͷར༻ྫ RISC-V࣮૷ͷRocket Chip
9. Chisel (Chisel 2)ͷߏ଄ Chiselຊମ(֤छܕఆٛΛఏڙ) RTLίʔυ (ChiselྲّྀͷScala) ςετίʔυ (Scala) ίʔσΟϯάϑΣʔζ
10. Chisel (Chisel 2)ͷߏ଄ ChiselϥϯλΠϜ RTLίʔυ (ChiselྲّྀͷScala) ςετίʔυ (Scala) ࣮ߦϑΣʔζ .vϑΝΠϧ .cppϑΝΠϧˠωΠςΟϒόΠφϦ ϑΝΠϧੜ੒ cycle-accurateͳςετ
11. Chisel≠ߴҐ߹੒ܥ
12. Chisel͸... εςʔτϚγϯͷࣗಈίϯύΠϧͳͲͯ͘͠Εͳ͍ ίʔυ͸ScalaͰॻ͕͘ɺ͋͘·Ͱ΋ճ࿏ੜ੒ίʔυ Λলྗهड़͢Δ΋ͷ
13. Chiselͷྑ͍ͱ͜Ζ IntelliJ IDEAͷࢧԉΛϑϧʹड͚ͭͭRTLίʔυΛॻ͚Δ γϯϘϧ໊ͷޡΓɺԋࢉʹ͓͚ΔܕෆҰகΛ͖ͬͪΓ ϦΞϧλΠϜͰԡ͑ͯ͘͞ΕΔɻϦϑΝΫλ΋ڧ͍ ௨ৗͷScalaίʔυͰγϛϡϨʔγϣϯ݁ՌΛݕূͰ͖Δ ग़ྗ͕Verilog HDLͳͷͰ͋ͪͪ͜΁࣋ͪग़͠΍͍͢ macOS/Windows/Linux্Ͱॻ͚Δ (େࣄ!)
14. ChiselͰॻ͍ͯMAX10΁
15. Chiselίʔυྫ(TMDSม׵ ൈਮ)
16. Simݕূίʔυ
17. Simݕূίʔυ
18. ScalaͬΆ͘ͳ͍͚ͲScalaͩ
19. ଞͷAlt-HDL(ࢀߟ) SFL(Structured Function description Language) ࢀߟ: https://ja.wikipedia.org/wiki/SFL Spinal HDL http://spinalhdl.github.io/SpinalDoc/ ChiselʹΩϨͨਓ͕࡞Γ࢝ΊͨΠϯεύΠΞܥ ϚϧνΫϩοΫαϙʔτڧ͍ɺεςʔτϚγϯهड़ࢧԉ͋Γ (ࣗಈతʹ੾ͬͯ͘ΕΔΘ͚Ͱ͸ͳ͍)
20. HDLੜ੒؀ڥʹ๬Ή΋ͷ ϚϧνϓϥοτϑΥʔϜαϙʔτ(macOS/Windows) ࣗ༝Ͱ྿Ձʹ࢖͑ͯࣗ༝ʹࣺͯΒΕΔ ϩοΫΠϯ, ϊʔαϯΩϡʔ. ΤσΟλαϙʔτ͕ڧ͍ ϗετݴޠͰςετΛॻ͍ͯγϛϡϨʔγϣϯݕূ
21. Chisel 2 → Chisel 3
22. Chisel 3ͷ ίʔσΟϯάϑΣʔζ Chiselຊମ(֤छܕఆٛΛఏڙ) RTLίʔυ (ChiselྲّྀͷScala) ςετίʔυ (Scala)
23. ωΠςΟϒόΠφϦ Chisel 3ͷ࣮ߦϑΣʔζ ChiselϥϯλΠϜ RTLίʔυ (ChiselྲّྀͷScala) ςετίʔυ (Scala) FIRRTL Verilator .fir .v cycle-accurateͳςετ
24. FIRRTL(ݴޠɾπʔϧڞ༻໊)
25. FIRRTLͷݴޠ࢓༷ https://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/ EECS-2016-9.pdf 50ϖʔδগʑ ·͋·͋෼͔Γ΍͍͢
26. FIRRTLΛखॻ͖ͯ͠ΈΔ circuit Top : module HalfAdder : input clk : Clock input reset : UInt<1> input io_a : UInt<1> input io_b : UInt<1> output io_s : UInt<1> output io_c : UInt<1> skip io_s <= xor(io_a, io_b) io_c <= and(io_a, io_b) module Top : input clk : Clock input reset : UInt<1> inst halfAdder of HalfAdder halfAdder.io_a is invalid halfAdder.io_b is invalid halfAdder.clk <= clk halfAdder.reset <= reset
27. FIRRTLΛखॻ͖ͯ͠Έͨ circuit͸ඞਢɺTop Level Module΋ඞਢ ػցతʹίʔυੜ੒͠΍ͦ͢͏ͳงғؾ͸͋Δ rocket.firΛಡΜͰΈΔͱɺϗετͱͷσόοά༻௨৴ͳͲΛຒΊͯΔ ৴߸Λ֎΁ग़ͯ͠σόοά͠΍͘͢͢Δͷ͸FIRRTLੜ੒ଆͷ੹೚? Chiselͷଞݴޠ൛Λ࡞࣮ͬͯ༻ΤϦΞ·Ͱ͍࣋ͬͯ͘ͷ͕໘౗ͦ͏ ͤΊͯඪ४ͷDUT௨৴ํ๏ΛܾΊ͓͍ͯͯ΄͍͠
28. ͦΕ͸ͦ͏ͱ
29. C#͕޷͖ (※ຊ୊)
30. FIRRTLͷͬ͘͟Γ࢓༷ ϑϧ൛ͱαϒηοτ൛(LoFIRRTL) ग़ྗλʔήοτ͸ओʹVerilog HDL ੜ੒ͨ͠Verilog HDLίʔυΛVerilator΁৯ΘͤͯC++ ΁ม׵͢Δ
31. FIRRTLͷC#ϑϩϯτΤϯυ Λ࡞ͬͨ
32. class HalfAdder : Module { public HalfAdder() { var io = new { a = new UInt(isOut: false), b = new UInt(isOut: false), s = new UInt(isOut: true), c = new UInt(isOut: true) }; this.io = io; io.s.Assign(io.a + io.b); io.c.Assign(io.a ^ io.b); } } public class AdderGenerator { public static void Main() { FirrtlSharp.Generator.GenerateHDL(new HalfAdder()); } }
33. ... module HalfAdder( input clk, input reset, input io_a, input io_b, output io_s, output io_c ); assign io_s = io_a & io_b; assign io_c = io_a ^ io_b; endmodule module TopHalfAdder( input clk, input reset ); wire halfadder_clk; wire halfadder_reset; ...
34. DEMO
35. FIRRTL ྑ͍ͱ͜Ζ ΍͸ΓػցతʹίʔυΛੜ੒͠΍͍͢ (High)FIRRTL→LoFIRRTLͷม׵εςοϓΛࠁΜͰ͍͚ Δ Verilog HDLΛੜ੒ͯ࢝͠ΊͯΤϥʔు͘ Ͱ͸ͳ͍ sourcemapͷ࢓૊ΈΛ͍࣋ͬͯΔ
36. FIRRTL ඍົͳͱ͜Ζ daemonϞʔυ͕ͳ͍ ϓϩηεىಈׂ͕ͱॏ͍ͷͰຖճىಈ͸ͨ͘͠ͳ͍ ϦΞϧλΠϜʹ͍ۙΤϥʔใࠂΛग़͍ͨ͠৔߹͸ঘߋ ϓϩηεؒ࿈ܞ͕͕ͬͭΓςΩετ? FIRRTLͷग़ྗΛparse͢Δͷ͸ෆໟ protobufͱ͔ɺͤΊͯJSONͰσʔλ࿈ܞͰ͖ͯ΄͍͠(ଟ෼ௐ΂͖ Εͯͳ͍͚ͩͰԿ͔͋Δ)
37. FIRRTL#ࢼ࡞൛ ྑ͍ͱ͜Ζ ֤ioϙʔτͷೖྗΛΤσΟλͰָʹิ׬Ͱ͖Δ ͦΕͳΓʹ؆ܿͳه๏ͰVerilog HDLΛੜ੒Ͱ͖Δ ஍ຯʹsourcemapαϙʔτͨ͠ ʮVerilog HDLม׵͕ίέͯΔ͜ͷίʔυɺ
 ɹC#ίʔυ֘౰Օॴ͸ͩ͜͜Αʯػೳ
38. FIRRTL#ࢼ࡞൛ ࢒೦ͳͱ͜Ζ
39. (C#ͷ)syntaxతͳࣄ৘ C#͸ϝιουݺͼग़͠΍incr/decrݺͼग़͠ͳͲΛߦ Θͳ͍ࣜͷΈͰจΛߏ੒ͤͯ͘͞Εͳ͍ io.s <= io.a + io.b;
 ͱ͍͏ه๏͸<=ͷԋࢉࢠΦʔόʔϩʔυͰ͸ϜϦ ݁Ռɺio.s.Assign(...)ͱ͍͏൵͍͠ײ͡ʹͳͬͨ
40. ࢼ࡞൛ͷ࣮૷໘(ࢼ࡞ͳͷͰ...) ࢒೦͕ൽΛඃͬͯΪϦΪϦಈ͍ͯΔ͙Β͍࢒೦ͷմ ςετػೳ΋౰વະ࣮૷ͩ͠ ΰϦԡ͠ίʔυͷҰ෦Λ͝ཡ͍ͩ͘͞ UIntҎ֎ͷܕΛ׬શແࢹ ioҎ֎ͷreg/wireΛແࢹ ৚݅෼ذΛແࢹ
41. ݁࿦
42. ṷ͸ṷ԰ɻDSLΛ࡞ΔͳΒɺ ޲͍ͨݴޠͰ΍Ζ͏ˠScala