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Basic Verilog
Kai-Chen Lin
Logic Design 2020
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Outline
• Login to a Server
• Download and Upload
• Basic Verilog
1. Module
2. Datatypes
3. Description
• Example
• Lab 1
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Login to a Server
Windows : Link Mac : Link
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Download and Upload
Windows : Link Mac : Link
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Basic Verilog - Module
Tutorial : Link
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Basic Verilog - Datatypes
REG
WIRE
v.s.
Tutorial : Link
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Basic Verilog - Description
Tutorial : Link
- Structure Description
- Dataflow Description
- Behavior Description
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Example
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Example
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Example
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Example
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Lab 1
Lab 1 : Link