Verlilog Lab 1 Tutorial

This is a basic Verilog tutorial for somebody who is interested in Logic Design.
In this talk, we will go through the basic knowledge of Verilog, including module definition, datatypes, three ways to describe a circuit and etc.
At the end of the talk, we will release Lab 1. The deadline for the lab is 4/13 2020.
Please submit your code to ILMS, NTHU.

Feel free to open a discussion on ILMS. I'll answer it as quickly as possible.

Kai-Chen Lin :)

Transcript

1. Basic Verilog Kai-Chen Lin Logic Design 2020
2. Outline • Login to a Server • Download and Upload • Basic Verilog 1. Module 2. Datatypes 3. Description • Example • Lab 1
3. Login to a Server Windows : Link Mac : Link
4. Download and Upload Windows : Link Mac : Link
5. Basic Verilog - Module Tutorial : Link
6. Basic Verilog - Datatypes REG WIRE v.s. Tutorial : Link
7. Basic Verilog - Description Tutorial : Link - Structure Description - Dataflow Description - Behavior Description
8. Example
9. Example
10. Example
11. Example
12. Lab 1 Lab 1 : Link