Logik A Free and Open-source FPGA Toolchain November 8, 2025 RTL ΛޠΔձ #18 Masanori Ogino 

ͳΜͩ͜Ε͸!? https://github.com/siliconcompiler/logik • 0.1.0 on March 18, 2025, 0.2.0 on October 21, 2025 • Yosys + Verilog-to-Routing (VtR) + FPGA Assembly (FASM) + OpenSTA static timing analyzer (!) • Wildebeest Yosys plugin 

ͳΜͳΜͩ͜Ε͸!? https://github.com/zeroasiccorp/wildebeest • “an open-source RTL synthesis tool that builds on the mature Yosys platform and extends it with advanced logic synthesis algorithms for state-of-the-art quality of results” • -opt ◦ “Specifies optimization mode [area, delay, fast] (default=area).” 

ͳΜ͔ͩ೉ͦ͠͏͚ͩͲʜʜ • Verilog-to-Routing (VtR) ʹରԠͤ͞Δඞཁ͋Γ ◦ Yosys ΤίγεςϜͰओྲྀͷ nextpnr Ͱ͸ͳ͍ • FASM ܦ༝ͷ bitstream ੜ੒ʹରԠͤ͞Δඞཁ͋Γ • ݱ࣌఺Ͱ͸ Zero ASIC ࣾͷ Platypus eFPGA ʹͷΈରԠ • ଞࣾͷ FPGA ΞʔΩςΫνϟʹҠ২Ͱ͖ͨΒ໘ന͍͔΋ʁ