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A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm CMOS with Digital Amplifier Technique

Yoshioka Lab (Keio CSG)
October 12, 2022
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A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm CMOS with Digital Amplifier Technique

Yoshioka Lab (Keio CSG)

October 12, 2022
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  1. 28.7: A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm

    CMOS with Digital Amplifier Technique © 2017 IEEE International Solid-State Circuits Conference 1 of 50 A 0.7V 12b 160MS/s 12.8fJ/conv- step Pipelined-SAR ADC in 28nm CMOS with Digital Amplifier Technique Kentaro Yoshioka, Tomohiko Sugimoto, Naoya Waki, Sinnyoung Kim, Daisuke Kurose, Hirotomo Ishii, Masanori Furuta, Akihide Sai and Tetsuro Itakura Toshiba Corporation, Kawasaki, Japan
  2. 28.7: A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm

    CMOS with Digital Amplifier Technique © 2017 IEEE International Solid-State Circuits Conference 2 of 50 Outline • Design target • Review of conventional ADCs • Digital amplifier technique • LA SAR technique • Measurement results • Conclusions
  3. 28.7: A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm

    CMOS with Digital Amplifier Technique © 2017 IEEE International Solid-State Circuits Conference 3 of 50 Outline • Design target • Review of conventional ADCs • Digital amplifier technique • LA SAR technique • Measurement results • Conclusions
  4. 28.7: A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm

    CMOS with Digital Amplifier Technique © 2017 IEEE International Solid-State Circuits Conference 4 of 50 Design Target • Next generation W-LAN (ex. IEEE 802.11ax) – 1024-QAM support • ADC requirements – High-speed (fs >100MS/s) – High-resolution (SNDR > 59dB) – Low-power (FoM<20fJ/conv.) • Include bias gen., reference buffer – Calibration-free • Minimize SoC startup time 256-QAM 1024-QAM
  5. 28.7: A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm

    CMOS with Digital Amplifier Technique © 2017 IEEE International Solid-State Circuits Conference 5 of 50 Outline • Design target • Review of conventional ADCs • Digital amplifier technique • LA SAR technique • Measurement results • Conclusions
  6. 28.7: A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm

    CMOS with Digital Amplifier Technique © 2017 IEEE International Solid-State Circuits Conference 6 of 50 High resolution SAR ADC C-DAC Vin Logic  ADC core low-power  Process scalable
  7. 28.7: A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm

    CMOS with Digital Amplifier Technique © 2017 IEEE International Solid-State Circuits Conference 7 of 50 High resolution SAR ADC  ADC core low-power  Process scalable  Power hungry reference ~4x core power [Liu, JSSC2016] C-DAC Vin Logic Vref Ref. buffer
  8. 28.7: A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm

    CMOS with Digital Amplifier Technique © 2017 IEEE International Solid-State Circuits Conference 8 of 50 Pipelined-SAR ADC  Relaxed Fine SAR resolution Relaxed ref. settling  Require high precision amplifiers [Furuta, ISSCC2010] Coarse ADC Amp. Fine SAR ADC Residue
  9. 28.7: A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm

    CMOS with Digital Amplifier Technique © 2017 IEEE International Solid-State Circuits Conference 9 of 50 SC Amplifier with OPAMP • Error occur with opamp non-idealities – Low gain with 28nmCMOS – Incomplete settling – Thermal noise A[dB] Amp. error THD [dB] 60 0.1% 67 40 1% 48 CF CS Vx OPAMP A=Loop-gain
  10. 28.7: A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm

    CMOS with Digital Amplifier Technique © 2017 IEEE International Solid-State Circuits Conference 10 of 50 SC Amplifier with OPAMP Tradeoff between power and accuracy • Error occur with opamp non-idealities – Low gain with 28nmCMOS – Incomplete settling – Thermal noise A[dB] Amp. error THD [dB] 60 0.1% 67 40 1% 48 CF CS Vx OPAMP A=Loop-gain
  11. 28.7: A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm

    CMOS with Digital Amplifier Technique © 2017 IEEE International Solid-State Circuits Conference 11 of 50 Conventional amplification methods  Tradeoff of power and accuracy Dynamic amp.  Gain calibration -Worsen SoC power efficiency Vx OPAMP
  12. 28.7: A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm

    CMOS with Digital Amplifier Technique © 2017 IEEE International Solid-State Circuits Conference 12 of 50 Digital Amplifier (DA) concept CS Vx DA CF Dynamic amp. Vx OPAMP  Tradeoff of power and accuracy  Gain calibration -Worsen SoC power efficiency 3x FoM improvement in high-speed cal-free ADCs DA cancels all errors of low-gain amplifier  Low-power  Calibration-free
  13. 28.7: A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm

    CMOS with Digital Amplifier Technique © 2017 IEEE International Solid-State Circuits Conference 13 of 50 Outline • Design target • Review of conventional ADCs • Digital amplifier technique – All-error canceling operation – Design methods and features • PVT enhancement techniques • Measurement results • Conclusions
  14. 28.7: A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm

    CMOS with Digital Amplifier Technique © 2017 IEEE International Solid-State Circuits Conference 14 of 50 All-error canceling concept Vx Ideal Vout 0 OPAMP errors CF CS Vx OPAMP Vout Time • Ideal amplification can be achieved by configuring Vout and converging Vx to zero [Fiorenza, ISSCC2006]
  15. 28.7: A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm

    CMOS with Digital Amplifier Technique © 2017 IEEE International Solid-State Circuits Conference 15 of 50 All-error canceling concept Vx Ideal Vout 0 OPAMP errors CF CS Vx Vout Sense • Low gain OPAMP errors sensed from Vx – Sense
  16. 28.7: A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm

    CMOS with Digital Amplifier Technique © 2017 IEEE International Solid-State Circuits Conference 16 of 50 All-error canceling concept Vx Ideal Vout 0 OPAMP errors CF CS Vx Vout Sense Feed- back • Low gain OPAMP errors sensed from Vx – Vout configured to converge Vx to zero – Sense FB
  17. 28.7: A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm

    CMOS with Digital Amplifier Technique © 2017 IEEE International Solid-State Circuits Conference 17 of 50 All-error canceling concept Vx Ideal Vout 0 OPAMP errors CF CS Vx OPAMP Vout Sense Feed- back • Low gain OPAMP errors sensed from Vx – Vout configured to converge Vx to zero – Obtain ideal amplification Sense FB
  18. 28.7: A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm

    CMOS with Digital Amplifier Technique © 2017 IEEE International Solid-State Circuits Conference 18 of 50 All-error canceling concept Vx Ideal Vout 0 OPAMP errors CF CS Vx OPAMP Vout Sense Feed- back Digital amp. How?? Minimum power, area, speed overhead • Sense FB
  19. 28.7: A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm

    CMOS with Digital Amplifier Technique © 2017 IEEE International Solid-State Circuits Conference 19 of 50 Digital Amplifier Implementation • Use successive approximation (SA)! – Low power, small, and fast in 28nmCMOS • All-error canceling – Comparator senses Vx errors – C-DAC configures Vout to converge Vx to zero • Digital Amp CF CS Vx Vout SA Logic Comp OP C-DAC
  20. 28.7: A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm

    CMOS with Digital Amplifier Technique © 2017 IEEE International Solid-State Circuits Conference 20 of 50 Digital Amplifier Operation CF CS Vx SA Logic Vout Comp 1. Opamp based amplification Opamp error 0 Vx Ideal Vout Vout fOP Comp fOP Time
  21. 28.7: A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm

    CMOS with Digital Amplifier Technique © 2017 IEEE International Solid-State Circuits Conference 21 of 50 Digital Amplifier Operation CF CS Vx SA Logic Vout Comp 2. Opamp switched off and start SA. 0 Vx Ideal Vout Vout fOP Comp Time
  22. 28.7: A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm

    CMOS with Digital Amplifier Technique © 2017 IEEE International Solid-State Circuits Conference 22 of 50 Digital Amplifier Operation 3. Judge polarity of Vx 0 Vx Ideal Vout Vout fOP Comp CF CS Vx SA Logic Vout Comp Time
  23. 28.7: A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm

    CMOS with Digital Amplifier Technique © 2017 IEEE International Solid-State Circuits Conference 23 of 50 Digital Amplifier Operation CF CS Vx SA Logic Vout Comp 4. Vx forced to zero by C-DAC switching 0 Vx Ideal Vout Vout fOP Comp Time
  24. 28.7: A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm

    CMOS with Digital Amplifier Technique © 2017 IEEE International Solid-State Circuits Conference 24 of 50 Digital Amplifier Operation CF CS Vx SA Logic Vout Comp Repeat polarity judge and switching 0 Vx Ideal Vout Vout fOP Comp Asynchronous Time
  25. 28.7: A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm

    CMOS with Digital Amplifier Technique © 2017 IEEE International Solid-State Circuits Conference 25 of 50 0 Vx Ideal Vout Vout fOP Comp Digital Amplifier Gain Error CF CS Vx SA Logic Vout Comp • Gain error decided by VCDACLSB – Irrelevant to intrinsic gain – Calibration-free amplifier in 28nm VCDACLSB CDAC LSB voltage Time
  26. 28.7: A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm

    CMOS with Digital Amplifier Technique © 2017 IEEE International Solid-State Circuits Conference 26 of 50 Outline • Design target • Review of conventional ADCs • Digital amplifier technique – All-error canceling operation – Design methods and features • PVT enhancement techniques • Measurement results • Conclusions
  27. 28.7: A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm

    CMOS with Digital Amplifier Technique © 2017 IEEE International Solid-State Circuits Conference 27 of 50 DA Design Methods • Gain error halved by increasing 1bit DA resolution (=halving VCDACLSB ) – Equivalent to boosting loop-gain by 6dB w/o DA w/DA Ideal loop-gain [dB] n=DA bit
  28. 28.7: A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm

    CMOS with Digital Amplifier Technique © 2017 IEEE International Solid-State Circuits Conference 28 of 50 DA Design Methods • Worst OPAMP loop-gain=20dB – Target loop-gain>60dB • With 7bit DA.. – 20dB+6dBx7bit=62dB! • Gain error halved by increasing 1bit DA resolution (=halving VCDACLSB ) – Equivalent to boosting loop-gain by 6dB w/o DA w/DA Ideal loop-gain [dB] Cubic enhancement n=DA bit
  29. 28.7: A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm

    CMOS with Digital Amplifier Technique © 2017 IEEE International Solid-State Circuits Conference 29 of 50 DA Design Methods • DA cancels all errors (e.g. settling errors) – Relax opamp slew current –  Improve power efficiency • Gain error halved by increasing 1bit DA resolution (=halving VCDACLSB ) – Equivalent to boosting loop-gain by 6dB w/o DA w/DA Ideal loop-gain [dB] Allowed OPAMP error - C-DAC range
  30. 28.7: A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm

    CMOS with Digital Amplifier Technique © 2017 IEEE International Solid-State Circuits Conference 30 of 50 DA Power Efficiency Analysis 0 0.25 0.5 0.75 1 30 40 50 60 70 Normalized power ADC SNDR [dB] [R. Demerow, Analog Dialogue, Volume 4-1, 1970] Time Output Conv. opamp
  31. 28.7: A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm

    CMOS with Digital Amplifier Technique © 2017 IEEE International Solid-State Circuits Conference 31 of 50 DA Power Efficiency Analysis • All-errors canceled if SError<C-DAC range • Can greatly relax OPAMP GBW 0 0.25 0.5 0.75 1 30 40 50 60 70 Normalized power ADC SNDR [dB] Infinite gain opamp w/o DA 20dB Loop-gain Opamp + 7b DA [R. Demerow, Analog Dialogue, Volume 4-1, 1970] Converges to ideal output even with large settling errors Time Output DA w/finite gain DA w/gain+settling error
  32. 28.7: A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm

    CMOS with Digital Amplifier Technique © 2017 IEEE International Solid-State Circuits Conference 32 of 50 DA Power Efficiency Analysis • All-errors canceled if SError<C-DAC range • Can greatly relax OPAMP GBW –  46% power savings 0 0.25 0.5 0.75 1 30 40 50 60 70 Normalized power ADC SNDR [dB] Infinite gain opamp w/o DA 20dB Loop-gain Opamp + 7b DA Break-even point of 7b DA in 28nm CMOS 46% [R. Demerow, Analog Dialogue, Volume 4-1, 1970] Designed point Converges to ideal output even with large settling errors Time Output DA w/finite gain DA w/gain+settling error
  33. 28.7: A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm

    CMOS with Digital Amplifier Technique © 2017 IEEE International Solid-State Circuits Conference 33 of 50 Circuit design requirements • Comparator offset = amplifier offset – Compensated by MDAC redundancy • Comparator noise dominant – Similar to 12b SAR ADC requirements – 160mVrms @Typ. • Low C-DAC linearity requirement – Only needs to be monotonic! • Reference buffer free – Small total capacitance ~300fF – Half than that of latter FSAR
  34. 28.7: A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm

    CMOS with Digital Amplifier Technique © 2017 IEEE International Solid-State Circuits Conference 34 of 50 Process scaling of DA • 65nm & 28nm DA-based 2.5b MDAC performance comparison – Both for SNDR~60dB Pipelined-ADC 65nm 28nm DA bit 6 8 Speed 40MS/s 80MS/s Power [uW/MS] 23 7.7 Area [mm2] 0.075 0.021 x2 x1/3 x1/3 Process scaling similar to Digital circuits 16nm.. 7nm..
  35. 28.7: A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm

    CMOS with Digital Amplifier Technique © 2017 IEEE International Solid-State Circuits Conference 35 of 50 Outline • Design target • Review of conventional ADCs • Digital amplifier technique • LA SAR technique • Measurement results • Conclusions
  36. 28.7: A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm

    CMOS with Digital Amplifier Technique © 2017 IEEE International Solid-State Circuits Conference 36 of 50 12b Pipelined-SAR ADC • Digital amplifier technique (DA) – Calibration-free amplifier in 28nm CMOS • Look ahead (LA) SAR – Speed enhancement technique 2.5b DA-based MDAC 10b+2b FSAR 3b LA SAR 3b MSB Ch.1 (80MS/s) Ch.2 (80MS/s)
  37. 28.7: A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm

    CMOS with Digital Amplifier Technique © 2017 IEEE International Solid-State Circuits Conference 37 of 50 Fine SAR design challenges DAFinish CompFSAR 12 cycles required MDAC Track Opamp DA Track 10b+2b FSAR Challenging to complete SAR conv. at slow PVTs 2.5b DA-based MDAC Sample
  38. 28.7: A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm

    CMOS with Digital Amplifier Technique © 2017 IEEE International Solid-State Circuits Conference 38 of 50 Look-ahead SAR technique FSAR 9 cycles w/LA 10b+2b FSAR 3b LA SAR 3b MSB 2.5b DA-based MDAC Ideal Vout DA
  39. 28.7: A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm

    CMOS with Digital Amplifier Technique © 2017 IEEE International Solid-State Circuits Conference 39 of 50 Look-ahead SAR technique FSAR 9 cycles w/LA 10b+2b FSAR 3b LA SAR 3b MSB 2.5b DA-based MDAC Ideal Vout DA Look ahead Vout Triggered by DA’s 3rd cycle completion signal
  40. 28.7: A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm

    CMOS with Digital Amplifier Technique © 2017 IEEE International Solid-State Circuits Conference 40 of 50 Look-ahead SAR technique FSAR 9 cycles w/LA 10b+2b FSAR 3b LA SAR 3b MSB 2.5b DA-based MDAC Ideal Vout DA Look ahead Vout FSAR sample final Vout
  41. 28.7: A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm

    CMOS with Digital Amplifier Technique © 2017 IEEE International Solid-State Circuits Conference 41 of 50 Look-ahead SAR technique • 30% speed improvement • Area overhead only 5% of FSAR • Power savings as in subrange SAR – 30% switching power cutdown • LA SAR noise, offset, mismatch effects compensated by FSAR redundancy [Tai, ISSCC2014]
  42. 28.7: A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm

    CMOS with Digital Amplifier Technique © 2017 IEEE International Solid-State Circuits Conference 42 of 50 Outline • Design target • Review of conventional ADCs • Digital amplifier technique • LA SAR technique • Measurement results • Conclusions
  43. 28.7: A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm

    CMOS with Digital Amplifier Technique © 2017 IEEE International Solid-State Circuits Conference 43 of 50 Chip Micrograph 28nm CMOS 0.097mm2 (Including decaps) Reference buffer not required Q-ch ADC I-ch ADC Interleave Ch.1 Interleave Ch.2 300um 320um 10b FSAR 2.5b MDAC LA SAR Decap TBCS
  44. 28.7: A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm

    CMOS with Digital Amplifier Technique © 2017 IEEE International Solid-State Circuits Conference 44 of 50 Temperature tolerance 50 54 58 62 66 -40 0 40 80 120 SNDR [dB] Temperature [℃] Sample 1 Sample 2 Sample 3 Measured@fs =160 MS/s fin =10.1 MHz SNDR>59.5dB achieved throughout -40~125℃ without calibration.
  45. 28.7: A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm

    CMOS with Digital Amplifier Technique © 2017 IEEE International Solid-State Circuits Conference 45 of 50 FFT results -1 -0.5 0 0.5 1 0 1000 2000 3000 4000 DNL [LSB] Codes -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 0 1000 2000 3000 4000 INL [LSB] Codes +0.86 -0.62 +1.48 -1.49 -140 -120 -100 -80 -60 -40 -20 0 0 20 40 60 80 Power [dBc] Frequency [MHz] HD2 HD3 HD4 HD5 HD6 HD7 Int. tone Fundamental 61.7 dB 63.0 dB 72.7 dB 160 MS/s 10.1 MHz 65536 SNDR: SNR: SFDR: fs : fin : Point:
  46. 28.7: A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm

    CMOS with Digital Amplifier Technique © 2017 IEEE International Solid-State Circuits Conference 46 of 50 5.E+00 5.E+01 5.E+02 1.E+07 1.E+08 1.E+09 FOMW,hf [fJ/conv-step] fsnyq [Hz] w/Gain Calibration wo/Gain Calibration Design target Benchmarking [Murmann, ADC Performance Survey] (Calibration presence surveyed by author) [1] [2] [6] Data From ISSCC&VLSI[3] (Pipelined&Pipelined-SAR ADC, SNDR>56dB)
  47. 28.7: A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm

    CMOS with Digital Amplifier Technique © 2017 IEEE International Solid-State Circuits Conference 47 of 50 5.E+00 5.E+01 5.E+02 1.E+07 1.E+08 1.E+09 FOMW,hf [fJ/conv-step] fsnyq [Hz] w/Gain Calibration wo/Gain Calibration This Work 3x Design target Data From ISSCC&VLSI[3] (Pipelined&Pipelined-SAR ADC, SNDR>56dB) [1] [2] [6] Benchmarking • >3x FoM improvement for fs >50MS/s SNDR>56dB cal-free pipelined ADCs [Murmann, ADC Performance Survey] (Calibration presence surveyed by author)
  48. 28.7: A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm

    CMOS with Digital Amplifier Technique © 2017 IEEE International Solid-State Circuits Conference 48 of 50 This work Verbruggen VLSI 2014[1] Zhou JSSC 2015[2] Chai ISSCC 2012[6] Supply [V] 0.7 0.9 1.1 1 Fs [MS/s] 160 200 160 200 SNDR@Nyq. [dB] 61.1 65 65.3 57 Power [mW] 1.9 2.3 5 5.4 FoMW [fJ/conv.] 12.8 7.9 20.7 46.4 Area [mm2] 0.097 (Inc. Decap) 0.35 (Inc. Decap) 1.87 (Inc. Decap) 0.19 Calibration? No Yes (Gain, etc.) Yes (Gain) No Benchmarking
  49. 28.7: A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm

    CMOS with Digital Amplifier Technique © 2017 IEEE International Solid-State Circuits Conference 49 of 50 Outline • Design target • Review of conventional ADCs • Digital amplifier technique • PVT enhancement techniques • Measurement results • Conclusions
  50. 28.7: A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm

    CMOS with Digital Amplifier Technique © 2017 IEEE International Solid-State Circuits Conference 50 of 50 Conclusions • Digital amplifier with all-error canceling – Effective loop-gain of over 60dB achieved with OPAMP loop-gain of only 20dB – Process scalability as digital circuits • LA SAR technique proposed to enhance the Fine SAR speed • 3x FoM improvement compared with similar high-speed cal-free pipelined ADCs