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Transactional Memory in Today's C++

Transactional Memory in Today's C++

A tech talk at Rackspace Atlanta.

Zhihao Yuan

May 29, 2013
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  1. A (mutual exclusive) lock is • a shared resource •

    waited by multiple threads • to enter a critical section.
  2. Lock as a shared resource is the root of all

    the contention.[1] • Fine-grained lock • Contention vs. overhead
  3. Locking as a runtime mechanism is an enemy to generic

    programming. • synchronized block in Java™ • Lock hierarchy
  4. I just want an atomic code block • No sharing

    • No waiting • Works with GP
  5. Available in GCC >= 4.7 • -fgnu-tm • libitm (Intel

    TM ABI[3]) • Implemented C++ TM Draft 1.1[4] • "If you observe performance that is lower than expected, you should not assume that transactional memory is inherently slow; instead, please just file a bug. "
  6. How it works? __transaction_atomic { // journal ++x; ++y; }

    // commit if validation passed // retry if failed
  7. How it works? __transaction_atomic { // journal ++x; ++y; }

    // commit if validation passed // retry if failed
  8. Ways to forbid • GCC partially knows • Code vs.

    Library Possible annotation approaches • [[transaction_safe]], [[transaction_unsafe]] • txunsafe, like noexcept
  9. Long answer __transaction_atomic is atomic, thus, the grouped operations are

    one operation without externally visible intermediate states. • Debugging: Schrödinger's cat • Local jumps are not allowed • Exception of integral type is allowed
  10. Interact with exceptions Draft 1.1 • noexcept • __transaction_cancel Wording

    V1 (not implemented yet) • [[noexcept]] • [[cancel_on_escape]] • [[commit_on_escape]]
  11. A __transaction_relaxed block is • Isolated (globally indeterminately sequenced) •

    Wait-free (no longer retry) • Composable (with both atomic and relaxed transactions) Conceptually, a global lock.
  12. Uses of __transaction_relaxed • Printf debugging :) ◦ Replacing __transaction_atomic

    with __transaction_relaxed does not change the behavior of a program. • Wrap a __transaction_atomic block to cancel an irrevocable operation
  13. Hardware TM on x86-64 • Intel Haswell architecture • Ship

    date: June the 1st week • XBEGIN, XEND, XABORT instructions • Fallback code path support
  14. So... 2005, first x86-64 dual core CPU; 2010, first dual

    core cellphone; 2013, first x86-64 CPU with HTM. Wait until your cell phone gets HTM?
  15. Links 1. Herb Sutter, "Sharing Is the Root of All

    Contention" http://www.drdobbs. com/architecture-and-design/sharing-is-the-root-of-all- contention/214100002 2. Richard T. Saunders, "Thread-safe and Thread-neutral Bags" http: //cppnow.org/files/2013/04/saunders_paper_cppnow2013.pdf 3. "Intel® Transactional Memory Compiler and Runtime Application Binary Interface", v1.1 http://gcc.gnu.org/wiki/TransactionalMemory? action=AttachFile&do=get&target=Intel-TM-ABI-1_1_20060506.pdf 4. "Draft Specification of Transactional Language Constructs for C++", v1. 1 https://sites.google.com/site/tmforcplusplus/C%2B% 2BTransactionalConstructs-1.1.pdf