Using fully open sourced toolchain to play RISC-V

Disclaimer :
Moving my slides to Speaker Desk since LinkedIn sold SlideShare.

This was the talk I introduced open source EDA toolchain and how to play a MCU level RISC-V core with such toolchain.

Transcript

1. The last mile of open source using fully open sourced toolchain to play RISC-V
2. For the record ...... • Don’t be too anticipated. – I have only myself, unemployed and dropped out.
3. It matters. • “Student's ARM7 clone disappears from Web” https://www.eetimes.com/document.asp?doc_id=1144157 I’m gonna repeat this over and over until ARM becomes the new MIPS. :-P
4. Pushing the boundry of “last miles” • Source code for software. • Source code for hardware. • Source code for the EDA tools.
5. RISC-V • Just a collection of ISA specs. – Not an implementation of it. • Not the very 1st “open” ISA either.
6. Different kind of “openess” • Source available, which is not exactly “open-sourcing.” – Lattice Mico8 is only permited to run on its own products. Source code license header has it that : • Lattice Semiconductor grants permission to use this code for use in synthesis for any Lattice programmable logic product. Other use of this code, including the selling or duplication of any portion is strictly prohibited. • Although there are some earlier copies of tool-generated LM8 is licensed under different license, it’s kinda in the twilight zone.
7. Different kind of “openess” (cont.) • Open source with patents – Vanilla OpenSPARC arguably contains parts protected by patents. • Clean room re-implementation. • Strip those allegedly patented parts. • Simply don’t care. (Military use. Sue me if you dare to.)
8. Different kind of “openess” (cont.) • (weak) Copyleft yet the license seems unfitting. – Original OpenRISC 1200 is licensed under LGPL. • How do you define terms like “object form” and “linking” for circuit designs ? Even you could give a definition, laws are born to be bent. • Attempts to make new (weak) copyleft license. – mor1kx, the newer implementation of OpenRISC 1000 ISA, distributes with Open Hardware Description License, which is based on Mozilla Public License 2.0 .
9. Different kind of “openess” (cont.) • Lattice Mico32 – “Lattice Semiconductor Corporation Open Source License” : The Provider grants to You a personal, non-exclusive right to use and distribute the source code of the Software provided that : • You make distributions free of charge under these license terms. • You ensure that the original copyright notices and limitations of liability and warranty sections remain intact.
10. License for famous open RISC-V cores Name License Rocket Apache 2.0 & 3-caluse BSD BOOM Apache 2.0 & 3-clause BSD RI5CY Solderpad Hardware License (based on APL 2) SweRV Apache 2.0 E200 Apache 2.0 PicoRV32 Internet Systems Consortium License (2-clause BSD) Most of them are licensed under permissive licenses.
11. Last mile to open source : EDA toolchain • Heavily hardware dependent. • Protected by licenses and patents. • Software plumber guys like me don’t do well at math & algo.
12. HDL-to-bitstream flow for Lattice iCE40 • yosys – Logic synthesis, to netlist. • arachne-pnr – Perform APR on netlist. • icepack – Bitstream generation. Verilog yosys Synthesis control script BLIF arachne-pnr tile info icepack bitstream
13. Crash course : verilog to netlist yosys -p ‘read_verilog fadd.v;\ synth_ice40 -top full_adder-blif fadd.blif’ module full_adder(a,b,cin,sum,cout); input a,b,cin; output reg sum,cout; always@(*) begin {cout,sum}=a+b+cin; end endmodule # Generated by Yosys 0.8 .model fulladder .inputs x y cin .outputs A cout .names $false .names $true 1 .names $undef .gate SB_LUT4 I0=y I1=x I2=cin I3=$false O=A .param LUT_INIT 10010110 .gate SB_LUT4 I0=y I1=x I2=cin I3=$false O=cout .param LUT_INIT 11101000 .end
14. Crash course : verilog to netlist (cont.) input output a b cin cout sum 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 1 1 0 1 0 0 0 1 0 1 1 0 1 1 0 0 1 1 1 0 1 1 1 1 1
15. Crash course : verilog to netlist (cont.) input output I3 I2 I1 I0 O 0 0 0 0 LUT_INIT[0] 0 0 0 1 LUT_INIT[1] 0 0 1 0 LUT_INIT[2] 0 0 1 1 LUT_INIT[3] 0 1 0 0 LUT_INIT[4] 0 1 0 1 LUT_INIT[5] 0 1 1 0 LUT_INIT[6] 0 1 1 1 LUT_INIT[7] 1 0 0 0 LUT_INIT[8] 1 0 0 1 LUT_INIT[9] 1 0 1 0 LUT_INIT[10] 1 0 1 1 LUT_INIT[11] 1 1 0 0 LUT_INIT[12] 1 1 0 1 LUT_INIT[13] 1 1 1 0 LUT_INIT[14] 1 1 1 1 LUT_INIT[15]
16. Crash course : verilog to netlist (cont.) input output I3 I2 I1 I0 O 0 0 0 0 LUT_INIT[0] 0 0 0 1 LUT_INIT[1] 0 0 1 0 LUT_INIT[2] 0 0 1 1 LUT_INIT[3] 0 1 0 0 LUT_INIT[4] 0 1 0 1 LUT_INIT[5] 0 1 1 0 LUT_INIT[6] 0 1 1 1 LUT_INIT[7] 1 0 0 0 LUT_INIT[8] 1 0 0 1 LUT_INIT[9] 1 0 1 0 LUT_INIT[10] 1 0 1 1 LUT_INIT[11] 1 1 0 0 LUT_INIT[12] 1 1 0 1 LUT_INIT[13] 1 1 1 0 LUT_INIT[14] 1 1 1 1 LUT_INIT[15] input output a b cin cout sum 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 1 1 0 1 0 0 0 1 0 1 1 0 1 1 0 0 1 1 1 0 1 1 1 1 1 .gate SB_LUT4 I0=y I1=x I2=cin I3=$false O=A .param LUT_INIT 10010110 .gate SB_LUT4 I0=y I1=x I2=cin I3=$false O=cout .param LUT_INIT 11101000
17. Yosys Open Synthesis Suite • BLIF : Berkeley Logic Interchange Format • RTLIL : RTL Intermediate Language Verilog frontend AST “frontend” AST VHDL frontend RTLIL Passes ilang frontend BLIF backend BLIF One of these passes is called : “techmap” , meaning “technology map” , which will load “gate” library and perform mapping. Several optimization passes are also available, e.g. flatten.
18. Yosys Open Synthesis Suite • BLIF : Berkeley Logic Interchange Format • RTLIL : RTL Intermediate Language Verilog frontend AST “frontend” AST VHDL frontend Passes ilang frontend BLIF backend BLIF One of these passes is called : “techmap” , meaning “technology map” , which will load “gate” library and perform mapping. Several optimization passes are also available, e.g. flatten. high level Common RTL Platform RTL
19. Yosys AST AST_MODULE <fadd.v:1> str='\full_adder' AST_WIRE <fadd.v:2> str='\a' input port=1 AST_WIRE <fadd.v:2> str='\b' input port=2 AST_WIRE <fadd.v:2> str='\cin' input port=3 AST_WIRE <fadd.v:3> str='\sum' output reg port=4 AST_WIRE <fadd.v:3> str='\cout' output reg port=5 AST_ALWAYS <fadd.v:5> AST_BLOCK <fadd.v:5> AST_BLOCK <fadd.v:7> AST_ASSIGN_EQ <fadd.v:7> AST_CONCAT <fadd.v:7> AST_IDENTIFIER <fadd.v:7> str='\sum' AST_IDENTIFIER <fadd.v:7> str='\cout' AST_ADD <fadd.v:7> AST_ADD <fadd.v:7> AST_IDENTIFIER <fadd.v:7> str='\a' AST_IDENTIFIER <fadd.v:7> str='\b' AST_IDENTIFIER <fadd.v:7> str='\cin' module full_adder(a,b,cin,sum,cout); input a,b,cin; output reg sum,cout; always@(*) begin {cout,sum}=a+b+cin; end endmodule
20. Technology Map • Yosys performs at least 2 turns of techmap for iCE40. – The 1st one maps high level logics into internal “common” cell library. – The 2nd one maps previous outcome into iCE40 cell techlib. • Yosys has two mapping method, simplemap and Berkeley- abc.
21. Yosys interactive shell • Last 3 pics are made by following command sequence : read_verilog fadd.v show synth_ice40 -run :coarse show synth_ice40 -run :check show • Dependency : xdot (for showing)
22. arachne-pnr • perform place-and-route based on chipdb & pcf (pin-out constrain file) : arachne-pnr -w fadd.pcf-d 8k -P ct256 fadd.blif -p fadd.pcf -o fadd.ascii – The output is plaintext file for tile information. icebox_explain could give fair details about it. .logic_tile 21 32 LC_5 0110100100000000 0000 LC_7 0001011100000000 0000
23. arachne-pnr (cont.) • Each tile contains 8 LCs (logic cells).
24. arachne-pnr (cont.)
25. arachne-pnr (cont.) ... B10 : 000000000000000000000000000001000001 0000 0011 0000100000 B11 : 000000000000000000000000000001001010 0000 1100 0000000000 ... B14 : 000000000000000000000000000001000001 0000 0101 0000000000 B15 : 000000000000000000000000000001001010 0000 0011 0000000100 .logic_tile 21 32 LC_5 0110100100000000 0000 LC_7 0001011100000000 0000
26. arachne-pnr (cont.) • Algorithms are in place.cc & route.cc .
27. icepack • To “pack” tile info into bitstream for iCE40, which is a stream of commands/data to tell iCE40 how LCs are configured. icepack fadd.ascii fadd.bin • iceunpack -vv fadd.bin could show some info.
28. icepack (cont.) • Magic header 0xFF00. Follows with comment section. A byte mark 0x7EAA997E starts actual bitstream sequence. • MSB : opcode • LSB : payload length
29. SUSHI • System fUllstack workSHop for the Insane • I’d like to let my fellow classmates and other juniors to get some quick crash course about hardware-software codesign – With inexpensive hardware and completely open source software. • I still can remember the days when I need to download Xilinx ISE which consumes several Gbs and get the license registered • And that antique Spartan board needs deposit. Simply WTF.
30. The Board • Lattice ICE40HX8K-B-EBVN (Breakout Board) https://www.mouser.tw/ProductDetail/Lattice/ICE40HX8K-B-EVN?qs=ooqgTKD20drSds2K %2FEAnQg== • Only $1661 NTD. • iCE40-HX8K-CT256 – 128KBits Block RAM – 7680 Logic Cells • Supported by open source toolchain.
31. The CPU • PicoRV32 – github – RV32I[MC] w/o CSR (Control & Status Registers) • Custom interrupt handling machenism and instructions. – No pipeline. Multicycle. – Less than 3,000 LoCs. – Silicon-proven by efabless with X-Fab foundry 180nm tech, using completely open source flow, Qflow . (Process Design Kit is inevitably closed-source.)
32. The Firmware • MicroPython – ported github – A Python(-subset) implementation that could run on MCUs. – Meet some preliminaries of an operating system.
33. LiteX • github • A SoC generation framework with user-friendly firmware- building & toolchain-downloading helper scripts. • Open source project as well. • Supported firmwares are carefully integrated into framework. • Peripherals are implemented in Migen FHDL, which is based on Python.
34. Migen FHDL • A HDL (framework). Equipped with its own simulation framework.
35. PicoRV32 : Arithmetic Logic Unit
36. PicoRV32 : Instr. Decoding • Decode sub t2, t0, t1 (t0~t2 <=> x5~x7) t2 = t0 - t1 f7 rs2 rs1 f3 rd op 0100000 00110 00101 000 00111 0110011
37. Some miscs • R0(zero) in RV is always 0. • If LSB 2 bits are not b’11, it must be compressed instr.
38. PicoRV32 : CPU State Machine cpu_state_fetch cpu_state_ld_rs1 cpu_state_ld_rs2 cpu_state_execute cpu_state_stmem cpu_state_ldmem cpu_state_trap
39. MicroPython Porting Issues • ISR : PicoRV32 has only limited functionallity. Custom machenism needed. crt0-picorv32.S: _irq (irq handler from vector) :
40. Live Demo • (fingers crossed)
41. Future work • Get modthread work on PicoRV32. – STM32 pybthread implementation is portable. The only target dependent code is __get_BASEPRI from ARM CMSIS lib and NVIC controlling code. • Bring sleep_ms() (in modutime) to work. – __WFI (wait for interupt) from CMSIS lib again .