Rusty VMs and Emulation

Writing a Chip-8 Emulator in Rust

Transcript

1. Rusty VMs & Emulation
2. RyanLevick itchyankles
4. VirtualMachine
5. … an emulation of a particular computer system … [that] operate[s] based on the computer architecture & functions of a real or hypothetical computer
6. Examples
7. Examples
8. Examples
10. Rustendo64
13. Rust is a systems programming language that runs blazingly fast, prevents segfaults, and guarantees thread safety.
14. So let’s emulate something!
15. CHIP-8
17. 4KB (4,096 bytes) RAM
18. Memory
19. 0xFFF (4095) 0x200 (512) 0x0 (0) Reserved CHIP-8 Program and Data Space
20. Memory
21. 16 general purpose 8-bit registers
22. Memory Registers
23. 1 special 16-bit register (I)
24. Memory Registers I
25. program counter
26. Memory Registers I PC
27. 2 special 8-bit delay & sound registers
28. Memory Registers I PC Delay Sound
29. stack with 16 16-bit values
30. Stack Pointer
31. Memory Registers I PC Delay Sound SP Stack
32. Memory Mapped Display
33. Video
34. So what’s a program look like?
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00100000 00110000 00110010 00001010 00110000 00110000 00110000 00110000 00110000 00110110 00110000 00100000 00110110 00110001 00100000 00110001 01100110 00100000 00111000 00110111 00100000 00110001 00110010 00100000 00110100 00110110 00100000 00110000 00110000 00100000 00110001 00110010 00100000 00110111 00111000 00100000 00110100 00110110 00100000 00110011 01100110 00100000 00110001 00110010 00100000 00111000 00110010 00100000 00110100 00110111 00100000 00110001 00100000 00100000 00100000 00001010 00110000 00110000 00110000 00110000 00110001 00110000 00111000 00001010 00110110 00111001 00100000 01100110 01100110 00001010 00110000 00110000 00110000 00110000 00110000 01100011 00110000 00100000 00110001 00110010 00100000 01100011 00110000 00100000 00110001 00110010 00100000 01100011 00111000 00100000 00110111 00111001 00100000 00110000 00110001 00100000 00110100 00111001 00100000 00110000 00110010 00100000 00110110 00111001 00100000 00110000 00110001 00100000 00110110 00110000 00100000 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00100000 01100101 01100101 00100000 00111000 00110000 00100000 00111000 00110000 00100000 00111000 00110000 00100000 00111000 00110000 00100000 00111000 00110000 00100000 00111000 00110000 00001010 00110000 00110000 00110000 00110000 00110000 01100110 00110000 00100000 00111000 00110000 00100000 00110000 00110000 00100000 00110000 00110000 00100000 00110000 00110000 00100000 00110000 00110000 00100000 00110000 00110000 00100000 00110110 01100010 00100000 00110010 00110000 00100000 00110110 01100011 00100000 00110000 00110000 00100000 01100001 00110010 00100000 01100101 01100001 00100000 01100100 01100010 00100000 01100011 00110001 00100000 00110111 01100011 00100000 00110000 00110001 00001010 00110000 00110000 00110000 00110000 00110001 00110000 00110000 00100000 00110011 01100011 00100000 00110010 00110000 00100000 00110001 00110010 00100000 01100110 01100011 00100000 00110110 01100001 00100000 00110000 00110000 00100000 00110000 00110000 00100000 01100101 01100101 00100000 00100000 00100000 00100000 00100000 00100000 00100000 00100000 00100000 00100000 00100000 00100000 00100000 00100000 00100000 00100000 00100000 00100000 00100000 00100000 00100000 00100000 00100000 00100000 00001010 00110000 00110000 00110000 00110000 00110001 00110000 00111000 00001010 00110000 00100000 00110000 00110000 00100000 00110000 00110000 00100000 00110000 00110000 00100000 00110000 00110000 00100000 00110110 01100010 00100000 00110010 00110000 00100000 00110110 01100011 00100000 00110000 00110000 00100000 01100001 00110010 00100000 01100101 01100001 00100000 01100100 01100010 00100000 01100011 00110001 00100000 00110111 01100011 00100000 00110000 00110001 00001010 00110000 00110000 00110000 00110000 00110001 00110000 00110000 00100000 00110011 01100011 00100000 00110010 00110000 00100000 00110001 00110010 00100000 01100110 01100011 00100000 00110110 01100001 00100000 00110000 00110000 00100000 00110000 00110000 00100000 01100101 01100101 00100000 00100000 00100000 00100000 00100000 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36. 73 a2 6b 0c 6c 3f 6d 0c a2 ea da b6 dc d6 6e 00 22 d4 66 03 68 02 60 60 f0 15 f0 07 30 00 12 1a c7 17 77 08 69 ff a2 f0 d6 71 a2 ea da b6 dc d6 60 01 e0 a1 7b fe 60 04 e0 a1 7b 02 60 1f 8b 02 da b6 60 0c e0 a1 7d fe 60 0d e0 a1 7d 02 60 1f 8d 02 dc d6 a2 f0 d6 71 86 84 87 94 60 3f 86 02 61 1f 87 12 46 00 12 78 46 3f 12 82 47 1f 69 ff 47 00 69 01 d6 71 12 2a 68 02 63 01 80 70 80 b5 12 8a 68 fe 63 0a 80 70 80 d5 3f 01 12 a2 61 02 80 15 3f 01 12 ba 80 15 3f 01 12 c8 80 15 3f 01 12 c2 60 20 f0 18 22 d4 8e 34 22 d4 66 3e 33 01 66 03 68 fe 33 01 68 02 12 16 79 ff 49 fe 69 ff 12 c8 79 01 49 02 69 01 60 04 f0 18 76 01 46 40 76 fe 12 6c a2 f2 fe 33 f2 65 f1 29 64 14 65 00 d4 55 74 15 f2 29 d4 55 00 ee 80 80 80 80 80 80 80 00 00 00 00 00 6b 20 6c 00 a2 ea db c1 7c 01 3c 20 12 fc 6a 00 00 ee
37. 73 a2 6b 0c 6c 3f 6d 0c a2 ea da b6 dc d6 6e 00 22 d4 66 03 68 02 60 60 f0 15 f0 07 30 00 12 1a c7 17 77 08 69 ff a2 f0 d6 71 a2 ea da b6 dc d6 60 01 e0 a1 7b fe 60 04 e0 a1 7b 02 60 1f 8b 02 da b6 60 0c e0 a1 7d fe 60 0d e0 a1 7d 02 60 1f 8d 02 dc d6 a2 f0 d6 71 86 84 87 94 60 3f 86 02 61 1f 87 12 46 00 12 78 46 3f 12 82 47 1f 69 ff 47 00 69 01 d6 71 12 2a 68 02 63 01 80 70 80 b5 12 8a 68 fe 63 0a 80 70 80 d5 3f 01 12 a2 61 02 80 15 3f 01 12 ba 80 15 3f 01 12 c8 80 15 3f 01 12 c2 60 20 f0 18 22 d4 8e 34 22 d4 66 3e 33 01 66 03 68 fe 33 01 68 02 12 16 79 ff 49 fe 69 ff 12 c8 79 01 49 02 69 01 60 04 f0 18 76 01 46 40 76 fe 12 6c a2 f2 fe 33 f2 65 f1 29 64 14 65 00 d4 55 74 15 f2 29 d4 55 00 ee 80 80 80 80 80 80 80 00 00 00 00 00 6b 20 6c 00 a2 ea db c1 7c 01 3c 20 12 fc 6a 00 00 ee
38. 73a2
41. 73a2 7XNN
42. Memory Registers I PC Delay Sound SP Stack 0
43. 73a2 7XNN
44. 0 + a2 = a2
45. Memory Registers I PC Delay Sound SP Stack a2
46. Read Instruction Interpret Instruction Execute Instruction Increment Program Counter Repeat
47. What kind of instructions are there?
48. Load
49. Jump
50. Add
51. Subtract
52. Bit Shift
53. Skip if Equal
54. Draw N bytes of Sprite Starting at Pixel Specified in Register X and Register Y
55. pub struct Chip8 { regs: [u8; NUM_GENERAL_PURPOSE_REGS], i_reg: u16, delay_timer_reg: u8, sound_timer_reg: u8, stack_pointer_reg: u8, program_counter_reg: u16, memory: [u8; MEMORY_SIZE], stack: [u16; NUM_STACK_FRAMES], key_to_wait_for: Option<u8>, keyboard: [bool; NUM_KEYS], pub display: Box<Display>, }
56. let mut computer = Chip8::new(program); loop { // Actual code throttles this loop to the // specified 60 instructions per second computer.cycle(); }
57. impl Chip8 { // ... pub fn cycle(&mut self) { let instruction = self.instruction(); self.program_counter_reg = self.run_instruction(&instruction); } // ... }
58. impl Chip8 { // ... fn instruction(&self) -> Instruction { let pc = self.program_counter_reg; let higher_order = self.memory[pc as usize] as u16; let lower_order = self.memory[(pc + 1) as usize] as u16; RawInstruction::new( (higher_order << 8) + lower_order ).to_instruction() } // ... }
59. pub enum Instruction { ClearDisplay, Return, Jump(Address), Call(Address), SkipIfEqualsByte(Register, u8), SkipIfNotEqualsByte(Register, u8), SkipIfEqual(Register, Register), LoadByte(Register, u8), AddByte(Register, u8), Move(Register, Register), // ... }
60. impl RawInstruction { // ... pub fn to_instruction(&self) -> Option<Instruction> { match self.xooo() { 0x0 => { match self.ooxx() { 0xE0 => Some(Instruction::ClearDisplay), 0xEE => Some(Instruction::Return), _ => None, } } 0x1 => Some(Instruction::Jump(self.oxxx())), 0x2 => Some(Instruction::Call(self.oxxx())), 0x3 => Some(Instruction::SkipIfEqualsByte(self.oxoo(), self.ooxx())), 0x4 => Some(Instruction::SkipIfNotEqualsByte(self.oxoo(), self.ooxx())), // ... } } // ... }
61. impl Chip8 { // ... fn run_instruction(&mut self, instruction: &Instruction) -> u16 { match *instruction { Instruction::ClearDisplay => { self.display.clear(); self.program_counter_reg + 2 } Instruction::Return => { let addr = self.stack[(self.stack_pointer_reg - 1) as usize]; self.stack_pointer_reg -= 1; addr + 2 } Instruction::Jump(addr) => addr, Instruction::Call(addr) => { self.stack_pointer_reg += 1; self.stack[(self.stack_pointer_reg - 1) as usize] = self.program_counter_reg; addr } //... } } // ... }
62. impl Chip8 { // ... fn run_instruction(&mut self, instruction: &Instruction) -> u16 { match *instruction { //... Instruction::AddByte(reg_number, value) => { let reg_value = self.read_reg(reg_number); self.load_reg( reg_number, value.wrapping_add(reg_value) ); self.program_counter_reg + 2 } //... } } // ... }
63. Graphics & Windowing
65. Glutin (alternative to GLFW)
66. for e in window { if let Some(_) = e.render_args() { let buffer = &computer.display.get_buffer(); draw_screen(buffer, &e); } if let Some(u) = e.update_args() { computer.cycle(u.dt); } }
67. fn draw_screen(display_buffer: &display::Buffer, window: &PistonWindow) { window.draw_2d(|context, graphics| { piston_window::clear(color::BLACK, graphics); for (y, row) in display_buffer.iter().enumerate() { for (x, &val) in row.iter().enumerate() { if val { let dimensions = [(x * ENLARGEMENT_FACTOR) as f64, (y * ENLARGEMENT_FACTOR) as f64, ENLARGEMENT_FACTOR as f64, ENLARGEMENT_FACTOR as f64]; Rectangle::new(color::WHITE) .draw( dimensions, &context.draw_state, context.transform, graphics ); } } } }) }
69. Thank you!
70. Sources
71. http://devernay.free.fr/hacks/chip8/C8TECH10.HTM https://en.wikipedia.org/wiki/CHIP-8 http://chip8.com http://mattmik.com/files/chip8/mastering/chip8.html