- segment fault is serious error… however segment is rarely used now • Page - page fault is not error, but may recall very slow disk access • The translation table is stored in TLB (movl cr3, eax) • IPC memory • Pipes • Process shared memory • With regard to IPC memory management, raptor uses mbuf and many ways to avoid copying
Address Bus and Data Bus — Bus clock cycle is several times slower than CPU clock • SDRAM and RDRAM are High bandwidth (throughput), High latency (100+ CPU cycles) • L1, L2, L3 caches — 90% of memory access is through cache • Multi-way cache lines: the more “ways” the more precise and more complicated circuit • DMA (direct memory access) mode: read from or write memory to device directly • Memory fences: loadload, loadsave, saveload, savesave, volatile (rb_gc_guarded_ptr_val)
(heap allocations) • Predicting performance (G1GC -XX:MaxGCPauseMillis) • Debugging (how to debug a segfault in GC?) • Pointer compressing (Jikes VM, LLVM compressing on linked list) • Language features (Erlang and Haskell take advantage of immutability) • Internal of C APIs (tcmalloc, jemalloc, … which to use?) • OS APIs (mmap) • (Disable) Compiler optimisations (volatile) • CPU arch (memory fence to ensure execution sequence)
optimize with C-ext — conservative GC makes C-ext easier to write • GIL, GC don’t need to add locks or spinlocks yet • Cross-architect requirement and code simplicity • GC provides tools for C-ext use