RISC-V CPU「TT-Ascalon」​

Tenstorrent Tech Talk #6, Session2

Transcript

1. RISC-V CPU「TT-Ascalon」 2026.2.25 Yohei Yamada Principal Engineer, RISC-V Cores 1
2. About Me 2 2023年 Tenstorrent入社 RISC-Vコア開発チームにて Ascalonコア開発に従事 - Fp pipeline - Vector pipeline - 浮動小数点演算機 - その他、タイミング最適化等 CONFIDENTIAL – CONTAINS TRADE SECRETS 山田洋平 担当箇所
3. Tenstorrent IP Portfolio RiscV CPU IP Application Processors • Ascalon • Alexandria • Babylon • Cyrene • Callandor Tensix AI IP • Tensix Blackhole • Tensix Neo • Tensix Neo Auto System IP • Memory & Interrupt Control: IOMMU, APLIC • System Management • Boot & Security • Debug & Test • SoC Internal Fabric • Chiplet D2D Interconnect Subsystem IP Compute Subsystem Reference • Ascalon CPU clusters • System IP • AI compute clusters OCA Harness
4. TT-Ascalon launch
5. TT-Ascalon High Performance RiscV is here!
6. RiscV is the Foundation for Tenstorrent Products Open architecture with mature system level specifications Modern instruction set architecture Strong ecosystem growth Community engagement BabyRisc (Tensix) CVA6 (Infra Enablement) Rocket (TT-NoC) EL2 (Security) BooM (Ocelot) X280 (AI SoC) Cores exist for most use cases except for high performance. Until now.
7. TT-Ascalon-X Disruptive high-performance RiscV processor • For infrastructure, datacenter, server and AI RVA23 2.5GHz SF4X High performance Vector Unit with 256b wide datapath Advanced branch prediction, prefetchers Virtualization, Security, Side channel mitigations, RAS GCC / LLVM support released TT-Ascalon-X Specs Available NOW! >21 SPECint2006/GHz >2.3 SPECint2017/GHz >4.1 SPECfp2017/GHz
8. Configurable Family Of Cores RiscV Processor Family
9. TT-Ascalon Cluster Configurable • 2-8 Cores • Shared L2 System IP components Interfaces • CHI-E (Coherent) • AXI5-Lite (Non-Coherent) • AXI4 (Management) Industry standard security functionality​ • Based on RiscV security primitives TT-Ascalon Cluster Specs
10. Customization Custom Instruction Support • Ref models • Toolchain Subsystem System IP Cluster Core ISA Core Microarchitecture Cluster Configuration Segment Targeted Features Segment Specific Topology
11. Ascalon - PL2 • Example of customization at a Cluster granularity ◦ Private L2 ◦ Custom cluster network to support a 1c design with a private L2 ◦ Scalable network to connect multiple such Cores together Core P-L2 Cluster Bridge Debug Trace N/W PM INT
12. Alexandria - High Performance CPU with Safety Architecture RVA23 Profile ASIL B/D Highly configurable Automotive and Robotics Alexandria Specs Releasing in Q3-2026
13. System IP Patch RAM Fuse Security controller RAS Boot & Safety Bridges AXI Bridge AXI Ring AXI Switch AXI Sizer CHI Overlay APLIC ACLINT Interrupt Controllers IOMMU System Management DM DTM JTAG-TAP Debug SMC Power Management PMNW Clock controller Reset controller Temp hub controller Cluster Wake & Shutdown Intf Indle Handler DST NTrace CLA Trace
14. Infrastructure Tools and Collateral Reference Platform Emulation Infra Tools Software Dev Kit Reference Model Memory Consistency Compliance Tests Verification Collateral Architectural Tools Silicon Tools Test Generator Coverage Model Testplans IOMMU Model APLIC Model Sim Trace Tool AX/CHI Transactor Models Silicon Compliance Tests PCIe Transactor PMON Recipe Open OCD Harness IP Trace Recipe 3rd party debug tool integration Toolchain Drivers* Software Optimization Guide CPL Firmware Open SBI Key Benchmarks Multi-vendor simulation recipes Formal Tool Recipe Batch Flows CI/CD Env Verilator Release HAPS Bitstream QEMU ZeBu Cloud Reference SOC Functional Platform “?”
15. Atlantis – Silicon Platform Highest performance RiscV development platform 8x Ascalon-X RiscV compliant System IP (IOMMU, APLIC) Enabling RiscV SW Ecosystem • Robotics & Automotive • Server • Networking • HPC • OS distro porting Atlantis Specs Available Q2-2026
16. Infrastructure Tools and Collateral Reference Platform Emulation Infra Tools Software Dev Kit Reference Model Memory Consistency Compliance Tests Verification Collateral Architectural Tools Silicon Tools Test Generator Coverage Model Testplans IOMMU Model APLIC Model Sim Trace Tool AX/CHI Transactor Models Silicon Compliance Tests PCIe Transactor PMON Recipe Open OCD Harness IP Trace Recipe 3rd party debug tool integration Toolchain Drivers* Software Optimization Guide CPL Firmware Open SBI Key Benchmarks Multi-vendor simulation recipes Formal Tool Recipe Batch Flows CI/CD Env Verilator Release HAPS Bitstream QEMU ZeBu Cloud Reference SOC Functional Platform Atlantis Board
17. Software Ecosystem is Ready for TT-Ascalon This would not have been possible without the community support of Ventana, Rivos, SiFive and many others!
18. High Performance CPU Roadmap Multi-generational roadmap | Silicon-proven IP Ascalon CPU >21 SPECint2006/GHz 2.5GHz SF4X System IP 2025 1st Gen CPU IP 2026 Automotive & 2nd Gen CPU IP 2027 & 2028 3rd Gen IP Deliverables Babylon CPU >22 SPECint2006/GHz, 3nm Atlantis 12nm ASC-X Silicon based development platform System IP ASIL-D IOMMU & APLIC, OCH, Multi-fabric support Cyrene CPU >25 SPECint2006/GHz System IP Next gen Server CPU Chiplet Production silicon Multi-cluster, 3nm Alexandria CPU ASIL-B/D, 3nm
19. Expanding RiscV HW Ecosystem • Coming Soon ◦ Support for Xiangshan Core ◦ E-trace support ◦ Expanded architectural tool support ▪ Ongoing ratified extensions ◦ Trainings and webinars to deploy open source tools ◦ Academic partnership and support
20. Tenstorrent RiscV IP is a Full Solution • Configurable core and cluster design • System IP • Reference models • Architectural tools • DV collateral With TT-RiscV IP – You Own Your Silicon Future It Is Not It Is • Silicon tools • SDK • Emulation platform support • Silicon platform • Open source support Just a core
21. Thank You
22. Appendix
23. Ascalon X Ascalon X Extreme Performance Disruptive high-performance RISC-V processor family for infrastructure, datacenter and AI • RVA23 compliant • RVV 1.0, 64-bit • Out-of-order, superscalar • Integrated trace and debug module • Integrated Interrupt controller, power management • Coherent and non-coherent interfaces • Application specific configurability • 2.5GHz+, SF4 • >21 SPECint2006/GHz Available NOW 0 5 10 15 20 25 Cortex A78 Ascalon S Cortex A710 Cortex A725 Cortex X3 Neoverse V2 Cortex X4 Neoverse V3 Ascalon X Cortex X925 SPECint2006 / GHz