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Thesis: A microkernel for the RISCV architecture

Thesis: A microkernel for the RISCV architecture

Cheesecake Labs

August 07, 2019
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  1. RISCV Instruction set architecture • Reduced Instruction Set Computer; •

    Started in 2010 by U.C Berkeley students; • Easily extensible; • Stable user ISA frozen in 2019; • Linux has ported RISCV; • Open-source; 2
  2. Microkernel • Provides a set of minimum services for the

    operating system to function; • Any other type of service is made from userspace; • Components are divided into a so-called servers; • A server may crash without affecting the system; • Easy to extend and mitigate problems; 3
  3. • Very little academic-oriented kernels; • No RISCV support; •

    Hard to learn in classes; • Very little POSIX support found; • Highly advanced embedded kernels available; ◦ FreeRTOS, etc; • Most have a custom libc support; The problem 5
  4. 6

  5. SiFive board 8 • Serial support; • FE310-G002; • Serial

    port communication; • WiFi/BLT support; • 32 Mbit Off-Chip (ISSI SPI Flash);
  6. The development environment • GCC 8.2.0; • Emacs; • GDB;

    • Platformio; • Minicom for serial communication; • GNU linker; • C language; • Assembly; • Python; 9
  7. Kernel requirements • Interrupt handler; • Round Robin scheduling algorithm;

    • Virtual memory space; • Minimal POSIX support; • Userspace support; • Basic GCC/C environment; • System management tools; 10
  8. Current kernel status • Port of Newlib (libc); ◦ Basic

    POSIX port • Basic interrupt handler; • Linear memory management support; • Physical Memory Protection; • In-software CPU initialization and configuration; • C environment; • UART/Serial communication; 11
  9. Next kernel steps • Process scheduling; • ELF execution environment;

    • Userspace memory management; • Microkernel server division; • Userspace server communication; 12