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RTL talk #18 dalance

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November 07, 2025
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RTL talk #18 dalance

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dalance

November 07, 2025

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Transcript

  1. ハードウェア記述言語 Veryl  特徴  合成可能RTLに最適化された構文  SystemVerilogとの相互運用性  生産性を高めるツール

     プロジェクト  2022/12~  822 GitHub Stars  18 contributors

  2. 今年のVeryl 0 10 20 30 40 50 60 70 80

    0 200 400 600 800 1000 1200 GitHub Star Webアクセス GitHub Star Webアクセス 2/25 FPGAマガジン誌 6/5 r/rust 6/1 技術書典 6/8, 13 VLSI Symposium 6/21 ISCA 8/2 SWoPP 8/25 HotChips 9/19 SNUG 10/7 DSF v0.16.5 v0.16.4 v0.16.3 v0.16.2 v0.16.1 v0.16.0 v0.14.1 v0.14.0 v0.13.5 v0.15.0 10/24 Interface誌

  3. 来年のVeryl  中間表現（Intermediate Representation）の導入  型チェックの強化  ネイティブシミュレータ  SDCの階層パスチェック

     GitHubのシンタックスハイライト  GitHub上に2000ファイル以上が必要  現在700くらいなので来年か再来年か？  宣伝活動  引き続き機会があれば