18th Panhellenic Conference on Informatics (PCI 2014)

Designing optimized forward residue number systems IP blocks converters from a network interface

Transcript

1. 1 Ioannis Petrousov petrousov@gmail.com Designing optimized forward residue number systems IP blocks converters from a network interface Minas Dasygenis mdasyg@ieee.org Department of Informatics and Telecommunications Engineering University of Western Macedonia, Kozani, Greece Presentation will be on github: • https://github.com/gpetrousov/pci2014_conference
2. 2 Presentation outline • Introduction – Our proposal – RNS basics – Related work • Tool architecture – Tool technologies – Web page – Detailed description ... • Output • Experimental results • Future work • Conclusions
3. 3 Introduction • Contemporary digital circuits demand a fast time to market period, and consequently a rapid prototype design exploration. • Most of these circuits are demanded to perform high bitwidth real time computations. • Binary arithmetic has reached its limits and researchers investigate other ways of increasing the computation speed. • The design automation and test processes (DAT) plays a crucial role. • One of the aspects of DAT is the fast parametrized generation of bit accurate models and their test vectors in a hardware description language (HDL).
4. 4 Our proposal • There are special architectures that operate accordingly to other arithmetic principles, like residue numbering system (RNS). • RNS has been proposed as a viable alternative to binary systems for achieving a very high throughput in cases where the dominant operations are multiplication and addition due to its carry free operation. • We created a unique web accessible tool that allows anyone to create custom parametrized binary to residue converters. • Our tool can generate a converter for any given prime number and any given input bit set. • The generated HDL codes are vendor neutral and can be synthesized either in an FPGA flow or in ASIC.
5. 5 RNS basics • A binary number has a unique representation in this system, when adhering to specific principles. • Given a set of relatively positive prime integers called the moduli set. • We define the dynamic range to be: • Any integer has a unique representation (m 1, m 2,... ,m n ) 0⩽X⩽M −1 M =∏ n 1 m i
6. 6 Related work • A lot of research is being done on Residue Numbering System. • Google Scholar yields more than 2,950,000 results. • To our best knowledge there is no similar tool that accepts parameters and generates optimal synthesizable VHDL architecture.
7. 7 Tool technologies • Utilizes several technologies: HTML, CSS, Javascript,... • Presents input forms to the user. • Validates the data.
8. 8 Tool webpage http://arch.icte.uowm.gr/hdl/bin2rnsFA.php
9. 9 User input
10. 10 User input • Input bits: any positive integer. This number determines the greatest number our converter will be able to process. • Moduli: any positive prime integer. Must be greater or equal to the greatest formable number above so the user don't get repeating results. • Test vectors: this number determines the amount of random test vectors to be created to test the correctness of the generated converter. • Pipeline: pipeline by a fixed way, by inserting D-flip flops. • VHDL & Schematic: the output can contain only the generated VHDL, or it can contain the code plus a schematic of the converter.
11. 11 Tool architecture • Our tool has a modular structure. • The binary to RNS tool consists of 3 main modules. • The modules are relatively abstracted and communicate with an intermediate netlist.
12. 12 Binary to RNS design module
13. 13 Binary to RNS design module • Consists of 3 stages. • Creates the intermediate net list format aHDL (abstracted HDL). • Components are placed in nodes. Each node carries a number of input vectors. • Inserts full-adders, half- adders, D-flip-flops at the appropriate positions.
14. 14 Recursion calculator • First stage. • Calculates the number of required recursions and the bitwidth after each recursion. • Example: input bits 8 moduli 5 Required Recursions: 3 Output bits of every recursion [8, 5, 4, 3]
15. 15 Bit reduction • Second stage • Designs the bit reduction architecture. • Reduces the number of input bits down to the number of moduli bits. • Uses recursive summations using carry save adder trees.
16. 16 Final mapping • Third stage. • Creates a structure of two paths. • First path is for the case where the output of the previous stage is greater than the moduli. In this case a substruction is performed. • Second path is for the case when no substraction is needed.
17. 17 HDL generator module
18. 18 HDL generator module • Consists of five submodules. 1. Validate the a-HDL netlist. 2. Create the definitions of input and output ports. 3. Create the signals and connect them to specific port numbers and types. 4. Generate the VHDL code. 5. Generate a schematic. This option takes more time to process.
19. 19 HDL testbench generator module
20. 20 HDL testbench generator module • Creates random vectors of testbenches in VHDL code, to test the correctness of the generated design. • For the number of test vectors: – For the number of used operands – Create random binary number – Extend it to full bitwidth – Precompute the correct result using the modulo operation – Insert the signal assignment for the input vectors, the wait statement for the result to be computed and the assert statement to test the output.
21. 21 HDL testbench generator module • The generated testbench code can be compiled and simulated. • The designer is not required to check the outputs manually. • Reports successful and failed simulation.
22. 22 Output
23. 23 Log file • The log file reports the process of the creation of the converter. • Displays a summary of the number of used components of the generated architecture. • Our tool works with the consideration of using as less components as possible to achieve the desired architecture.
24. 24 VHDL description • Sample case for – 8 input bits – 5 moduli – no pipeline
25. 25 VHDL library • Describes the components used in the architecture.
26. 26 Testbench • Sample testbench for – Input bits 8 – Moduli 5 – No pipeline
27. 27 Schematic • Input bits 3, moduli 3 and no pipeline.
28. 28 Experimental results • There are multiple methodologies to create RNS converters, but no publicly available tools. • For this reason, no comparison is provided. • We present a small portion of measurements.
29. 29 Sample results • Generated codes. • Performance measurements.
30. 30 Sample results • Synthesis results from Xilinx ISE 13.3 (Virtex6). • Pre synthesis estimation.
31. 31 Future work • Give the user the ability to create custom functions. • Create the rest of the line RNS converters and backward converters, like QRNS, RNS to binary. • Define the number of pipeline stages. • Generate output in other HDL languages, like Verilog. • Create an API so the tool can be used in a machine-to- machine scenario.
32. 32 Work in progress • We created a subtool which finds the most optimal combination of prime numbers to be used in the converter architecture. • This processes becomes computationally intensive for large numbers. • We have also developed the option to generate unique random testvectors for the testbench.
33. 33 Conclusions • Design automation and circuit verification are the foundation for increasing productivity and achieving fast time-to-market constraints. • We presented the first web accessible tool to create custom binary to residue converters. • Our tool outputs syntactically correct VHDL files, a custom automated testbench, a block schematic and other metrics. • The derived architectures are optimized designs. • Synthesis results indicate the high performance on the Xilinx Virtex 6 FPGA, with operational frequencies up to 783 Mhz. • The generated code is vendor neutral and can be synthesized in FPGA or in ASIC projects.
34. 34 Our tool is online Try our tool and give us feedback! http://arch.icte.uowm.gr/hdl/bin2rnsFA.php Presentation will be on github: https://github.com/gpetrousov/pci2014_conference