Automating the generation of hardware accelerators from custom arithmetic functions

Field programmable gate arrays (FPGAs) have become the standard for fast prototyping and evaluation of custom IP cores. However, the creation of complex circuits is a time consuming and error prone task with repeating procedures such as testing and verification. And even though there are several EDA tools which generate intellectual property (IP) blocks for specific purposes, to the best of our knowledge, there are no online tools able to design IP blocks from custom arithmetic functions. In this paper, we introduce our proof of concept (POC) circuit generator which is able to produce custom and verified hardware accelerators, specified in HDL, to speed up arbitrary integer arithmetic functions.

Transcript

1. Automating the generation of hardware accelerators from custom arithmetic functions Ioannis Petrousov petrousov@gmail.com Minas Dasygenis mdasyg@ieee.com University of Western Macedonia Department of Informatics and Telecommunications Engineering September 2017
2. Table of contents Introduction Theoretical background Software realization Frontend Backend Experimental results Conclusions and Future work September 2017 2 / 23
3. Introduction
4. Problem definition ▶ FPGAs are the standard for fast prototyping and applications where expandability is required. – Mars Exploration Rover (MER), Curiosity – Nuclear power plant's instrumentation and control – Automotive-related applications – Speed-up the conversion of radio frequency signals into decipherable information ▶ The creation of complex circuits is a time consuming and error prone task with repeating procedures (DSE, verification). ▶ Lack of online tools able to design IP blocks from custom arithmetic functions. September 2017 4 / 23
5. Our solution-proposal ▶ An online hardware generator able to dynamically create hardware descriptions from custom arithmetic functions. ▶ Completely custom input functions. – Contain as many variables and constants as desired – The bitwidth of the numbers is also custom defined ▶ Our tool is online and accessible from every common web browser. ▶ Requires no knowledge of a domain specific hardware description language. ▶ Generates syntactically correct VHDL descriptions. September 2017 5 / 23
6. Related work Tools ▶ MyHDL ▶ Xilinx ▶ Mathworks ▶ Spiral online tool ▶ FloPoCo Shortcomings ▶ Cost ▶ Require knowledge of DSL or programming language ▶ Require local installation ▶ Slow descriptions with many states September 2017 6 / 23
7. Theoretical background
8. Expression trees Construction algorithm f(x, y) = ((2 ∗ x) + y) September 2017 8 / 23
9. Technological stack Frontend ▶ HTML ▶ CSS ▶ Javascript Backend ▶ Python ▶ Cython ▶ JSON ▶ PHP September 2017 9 / 23
10. Software realization
11. General tool flow September 2017 11 / 23
12. Frontend
13. Input file ▶ JSON form ▶ Constructed from the user of computationally ▶ Function definition and variable bitwidths ▶ Communications between the frontend and backend { "function": "( ( in0 + in1 ) * ( in2 + 73 ) )", "in0": 2, "in1": 2, "in2": 5 } September 2017 13 / 23
14. Backend
15. α-HDL netlist netlist Properties ▶ Three-dimensional format ▶ Consists of 3 structures – components – interconnections – componentlist ▶ Generated automatically from the design unit ▶ Communication between units in the backend September 2017 15 / 23
16. Design module ▶ Constructs the α-HDL netlist ▶ Consists of 4 steps September 2017 16 / 23
17. HDL generator module September 2017 17 / 23
18. Testbench geneerator module Generates the testbenches which verify the functionality of the circuit. 1. For each variable, create random number 2. Lead the number into proper input port 3. Calculate the correct result 4. Compare the correct results with the ouput of the circuit Testbench example for the function f(x, y) = x + y September 2017 18 / 23
19. Generator output ▶ Circuit description in VHDL ▶ VHDL library with the sub-circuits Optionally: ▶ Circuit schematic (PNG and dot file) ▶ Testbench September 2017 19 / 23
20. Experimental results Table : Experimental results f(x, y) = ((2 ∗ x) + y). x bits y bits # slices Critical path (ns) Frequency (MHz) Power (W) 2 2 1 1.060 943,39 3.422 4 4 3 1.690 591.71 3.422 8 8 5 2.409 415.11 3.422 16 16 9 4.701 212.72 3.422 24 24 14 6.993 143 3.422 12 22 13 5.218 191.644 3.422 September 2017 20 / 23
21. Conclusions ▶ We created a tool which allows the conversion of custom mathematical functions into accelerators described in VHDL. ▶ Our generator is easily expandable. ▶ Facilitates Digital Space Explotation (DSE) ▶ Usage of Python for circuit generation. ▶ Calculation circuits do not rely on lookup tables (LUTs). ▶ No programming is required for the generation of an IP core. September 2017 21 / 23
22. Future work ▶ Add more generators. ▶ Add support for floating point numbers. ▶ Add pipeline support. ▶ Add expression tree schematic generator. September 2017 22 / 23
23. End of presentation Visit our tool online http://arch.icte.uowm.gr/hdl/equationparser_json.php