欧州での RISC-V と半導体振興策法、並びに Openchip との関係

𝗕𝗮𝗿𝗰𝗲𝗹𝗼𝗻𝗮 𝗦𝘂𝗽𝗲𝗿𝗰𝗼𝗺𝗽𝘂𝘁𝗲𝗿 𝗖𝗲𝗻𝘁𝗲𝗿 𝗮𝗻𝗱 𝗥𝗜𝗦𝗖-𝗩 𝗮𝗰𝘁𝗶𝘃𝗶𝘁𝗶𝗲𝘀 𝗶𝗻 𝘁𝗵𝗲 𝗘𝗨 𝘄𝗶𝘁𝗵 𝗢𝗽𝗲𝗻𝗰𝗵𝗶𝗽 𝗶𝗻𝘃𝗼𝗹𝘃𝗲𝗺𝗲𝗻𝘁
RISC-V Tech Study online meeting on April 18 Friday, 2025

欧州での RISC-V と半導体振興策法、並びに Openchip との関係
RISC-V勉強会@Online 2025/04/18 (金)のスライド

Transcript

1. 欧州の RISC-V 動向と半導体振興策法、並びに Openchip との関係 Akira Tsukamoto Openchip Fellow in Security and Ecosystem Architecture
2. OpenChip The Company BSC/NEC & Openchip Combining Power Game Changers RISC-V AI Interplay Vector & AI Openchip Accelerators Spreading RISC-V Go to Global
3. OpenChip The Company BSC/NEC & Openchip Combining Power Game Changers RISC-V AI Interplay Vector & AI Openchip Accelerators Spreading RISC-V Go to Global
4. Clients in 15 Countries - More than 1.500 high-tech projects GTD works across some of the most demanding industries, providing software, systems, and services for safety, mission, and business-cri tical applications. We provide our clients with secure, reliable technol ogy around the world. Out in space, our software orbits the Earth 24/ 7, 365 days a year. Closer to home, our software keeps aircraft flying high, makes vehicles safer, powers smart meter networks, and does much more. For over 34 years, we’ve been transforming the way th e world uses technology. IPCEI & DARE Programs Openchip & Software Technologies, S.L. Became operational in 2024 as a private company in Barcelona 4
5. Company Name Barcelona Supercomputing Center (BSC) とは 5 • BSC は欧州のスパコン共同事業である EuroHPC に指定された８拠点の一つ • 314 petaflops の MareNostrum 5 が稼動中 （HPC は High performance computing の略で一般的にはスパコンと同意語） • EuroHPC • 375 petaflops の LUMI (Finland)が一番高速、BSC (314 petaflops), Leonardo (Italy) が続く • 礼拝堂の地下にスパコンがあるのが特徴
6. Company Name BSC の現在 6 • 礼拝堂の地下 • MareNostrum 4 と Quantum Spain (量子コンピューター) の2種類のコンピューターが設置されていた • 今年に入り MareNostrum 4 は新しい量子コンピューター MareNostrum Ona設置のため撤去 • 今は量子コンピューター2台のみ • MareNostrum 5 はスペースの関係で隣接の新しい建物に設置 Quantum Spain はスペイン企業に よるデジタル式量子コンピューター NVIDIA Hopper GPU カード
7. Company Name BSC の過去(一部) MareNostrum 1 (2004) 42.3 TeraFlops 7 • MareNostrum 1 (2004) 42.3 TeraFlops IBM Power PC 970FX , 2406 node 9.6TB memory 200TB storage Myrinet & Gigabit Ethernet
8. Company Name BSC の過去 MARICEL (2011) 8 IBM Power 6 4GHz , 24 node IBM PowerXCell8 3.2GHz , 144 node 950GB memory 5TB storage PowerXCell8 は PlayStation 3 の Cell/B.E.CPU に 倍精度浮動小数点演算を追加
9. Company Name 欧州 の RISC-V プロジェクト 9 • Designing RISC-V-based Accelerators for next generation Computers (DRAC) project • BSCとカタルーニャ工科大学 (UPC) と共同にて、RISC-Vベースの次世代アクセラレーターを開発 • https://drac.bsc.es/en/home • Digital Autonomy with RISC-V in Europe (DARE) • 3 年計画, 38 の組織企業と連携, 240 million euros, EuroHPC を支援 • HPC (high performance computing) and AI (artificial intelligence) systems の試作 • 業界標準の chiplet と EU の最新半導体記述を活用 • Achieve maximum energy performance and efficiency • https://www.bsc.es/es/unete/oportunidades-de-excelencia-profesional/dare
10. Company Name EU委員会 (EU Commission) による Important Projects of Common European Interest （IPCEI）プロジェクト 10 • IPCEIは、EUの技術的主権を強化し、戦略的なバリューチェーンを構築するた めの重要な枠組み • 総額は910億ユーロ以上、加盟国の公的資金と民間投資が組み合わている • Openchip は 56 社の一つ https://competition-policy.ec.europa.eu/state-aid/ipcei/approved-ipceis_en • Openchip は、ファブレス半導体企業として、HPC（高性能コンピューティング）、 AI/ML/DL向けのアクセラレータチップを開発中。これらのチップは、最新のシ リコン技術（5nm未満）を採用し、RISC-Vアーキテクチャのもとで設計。 • Openchip は、GTD（スペインの技術企業）とバルセロナ・スーパーコンピュー ティング・センター（BSC）によって2021年に設立、2024年活動開始した。この 企業の目的は、ヨーロッパのデジタル主権を確立し、科学的発見を加速し、大 規模データの可視化やスマートサービスの提供を可能にすること。 • この取り組みは、EUのグリーンディールやデジタル変革戦略とも連携しており、 持続可能な技術開発を支援するものとなっている
11. Openchip Strategy to Develop a Global Market Openchip Corporate Development Strategy for European Union Expansion • Openchip is a Spanish Project truly multinational and multicultural: Europe is in our DNA. • +120 employees from 15 nationalities: Spain, Italy, Poland, Germany, France, UK, USA, Romania, Armenia, India, Pakistan, Ukraine, Japan, … • We are determined to promote the collaboration within EU countries: Hiring a talented team, distributing R&D facilities and having a point of presence next to our priority customers. • Company HQ is located in Barcelona, Spain, a global hub for business. • We aim to lead the efforts of European Union for Digital Sovereignty and adoption of RISC-V as the ISA for Supercomputing and Artificial Intelligence. 11
12. Cesc Guim – CEO PhD HPC – 60 publications +530 Patents 5 Years at Barcelona Supercomputing Center 17 Years Silicon and System Design at Intel Marc Fernández - CFO Bachelor in BA, MBA ESADE, Postgraduate degree in Law +25 years in Finance, Consulting and General Management Ingacio Astilleros – CSO Bachelor Physics, MBA IE. Master in Economy & Innovation. 4 patents. +25 years Sales, BizDev. & Management. INDRA, Sun Microsystems, Huawei, Intel. Tommaso Vali – Chief HW Eng. Master Degree in Electronic engineering 15 publications, 263 Patents, >30 Tapeouts, 35 Years of Silicon and System Design at Texas Instruments(10Y), Micron and Intel (25Y) Violante Moschiano – Chief HW Arch Master Degree in Electronic Engineering +350 Patents, 10 publications, ISSCC ITC, 20 Years of DTCD, System Design & Architecture . Micron and Intel Edgar Gonzàlez – Chief SW & AI Off. PhD AI – 27 publications, 4 patents 20 Years AI, ML, and NLP 12 Years as production SW team lead (Google Research, Cloud & Assistant) Gaspar Mora - CTO PhD Computer Architecture - 14 Patents 15 Years Silicon and System Architecture at Intel (Xeon, HPC’s Intel Omnipath) and Nvidia (GPU memory system) Ivan Rodero – Chief of Innovation PhD HPC – over 180 publications 5 Years at Barcelona Supercomputing Center 20 Years High-Performance Computing and world-class Advanced Cyberinfrastructure Satoru Tagaya – Chief HPC Architect y Senior Fellow MS in Computer Science 10 Patents 30 Years of Vector Computer System Architecture and Microarchitecture (SX series and SX Aurora) at NEC Corporation in Tokyo. Therese Jamaa, VP Strategic Alliances (Marketing, Communications, BD, RSC) Information Security, Business Administration, Marketing, Coach. Sema Group Schlumberger, Vodafone, Qualcomm, GSMA, Huawei. +25year experience Product Chief Officer -- VP EMBA from London Business School and a Meng in Telcom. University of Cantabria. 25 years in Semiconductor industry industries at Alcatel Bel, Lucent Microelectronics, Nokia, Chief Executive Office & C-Level Staff (holding +1300 patents in computer architecture and silicon engineering, +30 successful tape-outs) VPs, Fellows and Senior Fellows Akira Tsukamoto – Fellow in Security and Ecosystem Architecture Master of Science Degree in Computer Science Co-Chair of IoT Security Working Group at IETF +20 years of Developments, Cell/B.E. ARM Erich Focht – Chief HPC Software Architect and Fellow PhD HPC – 70 publications 27 Years at NEC contributing to tens of Top HPC 500 computers, system designs and algorithms. 12
13. OpenChip The Company BSC/NEC & Openchip Combining Power Game Changers RISC-V AI Interplay Vector & AI Openchip Accelerators Spreading RISC-V Go to Global
14. 14 14 History of Supercomputing short vector SIMD Earth Simulator Accelerators SIMT Earth Simulator 1984 1974 CDC STAR-100 CRAY-1 NEC SX-2 NEC SX-3 Vector Systems microprocessors Top 500 ✓ Vector systems were the general purpose supercomputers from the 1970s to beginning of 2000s. ✓ Dennard scaling and Moore‘s law pushed general purpose microprocessors to the top for ~15-20 years. ✓ Short vector SIMD: return of vector in general purpose processors: until now. ✓ End of Moore‘s law: shift to accelerators, SIMD (Xeon PHI) and SIMT (GPUs) + increasingly higher power. ✓ SIMT can be mapped to SIMD (vector) Slide courtesy of Dr. Erich Focht
15. 15 ✓ Progress comes from – Technology node – Tensor units – Numeric precision reduction – Structural (fake) sparsity – Blackwell: block scaled numeric formats 15 End of Moore‘s Law vs. AI Marketing Machine
16. 16 16 Long Vector Systems Evolution CDC STAR-100 First commercial vector 1974 – 100 MFLOPS Streaming from memory to memory 16 Bytes/FLOP CRAY-1 Commercially successful vector! 1976 – 160 MFLOPS - Vector registers! - Vector length: 64 elements - 16 Bytes/FLOP - Excellent scalar performance - Pipelined vector ops - Chained operations NEC SX-Aurora Tsubasa First vector accelerator card 2018 – 2.45 TFLOPS (DP) - 16nm - 8 – 10 cores - 6 x HBM2 (48 GB) - 1.2 – 1.55 TB/s mem BW - VL = 256 DP elements - 32 vector lanes 2022 – 4.9 TFLOPS (DP) - 7nm - 16 cores - 6 x HBM2e (96 GB) - 2.4 TB/s mem BW NEC Innovations: Multi-lane pipelines, vector cache, multi-core, ... Slide courtesy of Dr. Erich Focht
17. 17 ✓ Classical long vectors are excellent in handling data level parallelism (DLP) – One instruction keeps the pipeline(s) busy for long time – Hide latency of memory access through long vectors, temporal execution – Less sensitive to occasional latency increase (like NoC congestion) – Parallelism explicit, in the ISA! 17 From Vector To SIMD And Back CRAY-1 style vector pipeline Long Vector NEC SX-4 style parallel vector pipeline Long Vector AVX2 style SIMD pipeline Short Vector ✓ SIMD & short vectors – Cache/prefetch/OoO to hide latency – More difficult to keep pipelines full – Moderate DLP handling – Sensitive to latency increase – Good with short vectors Slide courtesy of Dr. Erich Focht
18. 18 ✓ Can implement SIMD, short vector, long vector with same ISA! ✓ Data parallelism → Loop vectorization ✓ Code ported to RISCV long vector runs on short vector cores, too. ✓ Investment is protected! RISC-V Vector Implementations: o Long vectors: Vitruvius, Ara, (Hwacha) o Short vectors: Spatz, Saturn, commercial 18 Vector is the better ISA RISC-V decided for a VECTOR ISA • Not a SIMD ISA! • Variable vector length o Vector length register like SX Aurora • Vector register size not prescribed o VLEN = VREG size in bits, is not fixed! o Left to the implementation o Must be power of 2 o ELEN ≥ 8 max element size in bits o ELEN ≤ VLEN ≤ 65536 Code can be VLEN agnostic! Runs on any implementation of RISCV Vector. https://github.com/riscv/riscv-v-spec NOTE: ARM SVE (Scalable Vector Extension) allows implementing 128-2048bit SIMD units.
19. 19 ✓Multi-purpose AI & HPC – Scale up & down ✓Balanced – Vector performance – Tensor/Matrix – Memory bandwidth ✓Usability, programmability ✓Accelerator capabilities with CPU-alike usability ✓RISC-V ecosystem 19 Positioning Usability / Programmability Performance area ~ memory bandwidth CPU VEC GPU
20. Processing Vector and GPGPU with RISC-V Vector: Small number of decently parallel operations • Flexible use model • More power efficient: • Single control for certain volume of computation GPU: A huge number of single threads • Generally Inflexible use model • Less power efficient: • Control for each computation thread required 20
21. OpenChip The Company BSC/NEC & Openchip Combining Power Game Changers RISC-V AI Interplay Vector & AI Openchip Accelerators Spreading RISC-V Go to Global
22. OpenChip provides: Silicon & Accelerators (e.g. PCIE) HPC Vector and AI Accelerators OpenChip provides: Reference Desings List of OEMS/ODMS validated implementations OpenChip provides: Baseline SDKS Advanced Management and Observability tools OpenChip provides: Application Optimization Services Modeling and system design What do we deliver? OpenChip System Centric Company OpenChip Business Plan Silicon Design PCB (PCIE etc.) Host, HW Platform & Chassis HPC Applications Software (Management, SDK, etc.) 22
23. Openchip Business Units Vector & AI Our strategic relationship with Barcelona Supercomputing Center and other Industry leaders like the Japanese NEC and other ecosystem partner, will help us build SoC´s for the most demanding environments of supercomputing, focusing on Vector processing and Artificial Intelligence. Secure & Efficient AI Better performance per watt. Drastic reduction of carbon footprint. Secure by design, our SoC´s will provide a full stack of technologies to secure the cloud and guarantee the privacy of the data and the digital sovereignty. Artificial Intelligence LLM (GPT) modes: Inference and training. HPC HPC-DC-Cloud Edge & IoT Openchip´s ability to combine in a SOC multiple chiplets with open interconnection (UCIe) can help to provide flexibility and shorter time to market of innovation. The adoption of RISC-V cores based on an instruction-set free of license can help to reduce costs, provide energy savings and access a wide ecosystem of applications that is being massively adopted in multiple industries. Openchip, being AI centric, will design their products by combining RISC-V with AI accelerators, Security Processors, Vector Processors and other accelerated chiplets. Born with an open philosophy, Openchip is developing strategic agreements with global silicon industry leaders and will develop in-house some accelerators in cooperation with Spanish & European R&D centers and Academia. 23
24. Production strategy Implementing BSC Vector Interface and Architecture RISC-V Core VPU OpenChip Production Enhancing Product VPU RISC-V Core VPU++ VPU-AB Next Gen. RISC-V + Vector COMBINING ADVANCED R&D WITH HIGH-END PRODUCTS A-GEN: Scientific ++ B-GEN: AI enhancements (Training & Inf) VPU-A ✓ Flexible Arch ✓ Intuitive SW Programming model ✓ Balanced FLOPS/W and Byte/FLOP 24 24
25. Openchip: Cultivating a Global Iron Triangle On becoming a Global Leader • Openchip & NEC represent an example of competitive technologies that, combined, could bring a unique value proposition to address multiple markets: EU, JP and US. • The alliance between these three innovative companies is, in fact, a strength that beyond Innovation and Technology, brings the values of Resilience and Trust. This information is disclosed under NDA 25
26. Thanks!