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Introdução a FPGA na prática

Introdução a FPGA na prática

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Tiago Martins

April 01, 2017
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  1. Lógica programável Programmable Read-Only Memory Programmable Logic Array Programmable Array

    Logic Generic Array Logic Complex Programmable Logic Device Field Programmable Gate Array 3 . 2
  2. Generic Array Logic (GAL) Portas AND e OR fixas Plano

    AND programável por EEPROM 3 . 6
  3. NOT F = A VHDL: INPUT OUTPUT A F 0

    1 1 0 F <= not A; 4 . 3
  4. AND F = A • B VHDL: INPUT OUTPUT A

    B F 0 0 0 0 1 0 1 0 0 1 1 1 F <= A and B; 4 . 4
  5. OR F = A + B VHDL: INPUT OUTPUT A

    B F 0 0 0 0 1 1 1 0 1 1 1 1 F <= A or B; 4 . 5
  6. XOR F = A ⊕ B VHDL: INPUT OUTPUT A

    B F 0 0 0 0 1 1 1 0 1 1 1 0 F <= A xor B; 4 . 6
  7. NAND F = A • B VHDL: INPUT OUTPUT A

    B F 0 0 1 0 1 1 1 0 1 1 1 0 F <= A nand B; 4 . 7
  8. NOR F = A + B VHDL: INPUT OUTPUT A

    B F 0 0 1 0 1 0 1 0 0 1 1 0 F <= A nor B; 4 . 8
  9. XNOR F = A ⊕ B VHDL: INPUT OUTPUT A

    B F 0 0 1 0 1 0 1 0 0 1 1 1 F <= A xnor B; 4 . 9
  10. Flip-flop tipo D Clock D Qnext Rising edge 0 0

    Rising edge 1 1 Non-Rising X Q 5 . 2
  11. Inputs Outputs A B C S 0 0 0 0

    1 0 0 1 0 1 0 1 1 1 1 0 Meio somador S <= A xor B; C <= A and B; 5 . 4
  12. Somador Completo Inputs Outputs A B Cin Cout S 0

    0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 5 . 5
  13. Somador Completo VHDL: Sh <= A xor B; S <=

    Sh xor Cin; C <= (Sh and Cin) or (A and B); 5 . 6
  14. VHDL VHSIC (Very High Speed Integrated Circuit) Hardware Description Language

    1980/1981 U.S. Department of Defense (DOD) 1983 IBM, Texas Instruments e Intermetrics O DOD determinou que todos os circuitos eletrônicos digitais deveriam ser descritos em VHDL F22 foi desenvolvido usando VHDL (7 FPGA e 1 ASIC) Padrão IEEE em 1987, revisado em 1993, 2008. 6 . 2
  15. VHDL - Estrutura Entity Entradas e saídas Architecture Funcionamento do

    bloco Suporte a multiplas arquiteturas Configuration Seleção da arquitetura Package Declarações comuns a multiplas unidades 6 . 3
  16. VHDL - Entidade entity black_box is port ( A :

    in std_logic; B : in std_logic; Z : out std_logic ); end entity black_box; 6 . 4
  17. VHDL - Entradas e Saídas IN Conecta-se a OUT ou

    INOUT OUT Conecta-se a IN ou INOUT INOUT Conecta-se a IN ou OUT ou INOUT BUFFER Conecta-se somente a buffer 6 . 5
  18. VHDL - Tipos library ieee; use ieee.std_logic_1164.all; bit ('0', '1')

    bit_vector(0 to 7) ('0', '1') boolean (true, false) integer (-231, 231-1) std_logic ('0', '1', 'X', 'Z', 'U', 'W', 'L', 'H', '-') std_logic_vector(15 downto 0) ('0', '1', 'X', 'Z', 'U', 'W', 'L', 'H', '-') 6 . 6
  19. VHDL - std_logic 'U' - não inicializado 'Z' - alta

    impedância 'X' - não conhecido '0' - valor lógico 0 '1' - valor lógico 1 'W' - signal fraco não conhecido 'L' - signal fraco tendendo a 0 'H' - signal fraco tendendo a 1 '-' - não interessa 6 . 7
  20. VHDL - Arquitetura Structural Portas e fios Register Transfer Level

    (RTL) Abstração em nível de registradores Descrição em circuitos combinacionais e síncronos Behavioral Descreve o comportamento e não as portas lógicas 6 . 8
  21. VHDL - Arquitetura architecture data_flow of black_box is signal x

    : std_logic; -- Não utilizado nesse exemplo begin Z <= A nand B; end architecture data_flow; 6 . 9
  22. VHDL - Tipos para operações aritméticas use ieee.numeric_std.all; unsigned(0 to

    15) ('0', '1', 'X', 'Z', 'U', 'W', 'L', 'H', '-') signed(31 downto 0) ('0', '1', 'X', 'Z', 'U', 'W', 'L', 'H', '-') 6 . 10
  23. VHDL - Somador completo library ieee; use ieee.std_logic_1164.all; entity fulladder

    is port ( x : in std_logic; y : in std_logic; c_in : in std_logic; s : out std_logic; c_out : out std_logic ); end entity fulladder; architecture rtl of fulladder is begin s <= x xor y xor c_in; c_out <= (x and y) or (c_in and x) or (c_in and y); end architecture rtl; 6 . 11
  24. VHDL - Flip-Flop library ieee; use ieee.std_logic_1164.all; entity flip_flop is

    port ( clk : in std_logic; rst : in std_logic; d : in std_logic; q : out std_logic ); end entity flip_flop; architecture rtl of flip_flop is begin process (rst, clk) begin if rst = '1' then q <= '0'; elsif rising_edge(clk) then q <= d; end if; end process; end architecture rtl; 6 . 12
  25. VHDL - Somador library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity

    adder_4_bit is port ( a : in std_logic_vector(3 downto 0); b : in std_logic_vector(3 downto 0); s : out std_logic_vector(3 downto 0); c_out : out std_logic ); end entity adder_4_bit; architecture rtl of adder_4_bit is signal arg_a : unsigned(3 downto 0); signal arg_b : unsigned(3 downto 0); signal sum : unsigned(4 downto 0); begin arg_a <= '0' & unsigned(a); arg_b <= '0' & unsigned(b); sum <= arg_a + arg_b; s <= std_logic_vector(sum(3 downto 0)); c_out <= sum(4); end architecture rtl; 8 . 3
  26. VHDL - Contador library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity

    counter_8 is port ( clk : in std_logic; rst : in std_logic; count : out std_logic_vector(7 downto 0) ); end entity counter_8; architecture rtl of counter_8 is signal counter : unsigned(7 downto 0); begin process (rst, clk) begin if rst = '1' then counter <= (others => '0'); elsif rising_edge(clk) then counter <= counter + 1; end if; end process; count <= std_logic_vector(counter); end architecture rtl; 8 . 4