1980/1981 U.S. Department of Defense (DOD) 1983 IBM, Texas Instruments e Intermetrics O DOD determinou que todos os circuitos eletrônicos digitais deveriam ser descritos em VHDL F22 foi desenvolvido usando VHDL (7 FPGA e 1 ASIC) Padrão IEEE em 1987, revisado em 1993, 2008. 6 . 2
impedância 'X' - não conhecido '0' - valor lógico 0 '1' - valor lógico 1 'W' - signal fraco não conhecido 'L' - signal fraco tendendo a 0 'H' - signal fraco tendendo a 1 '-' - não interessa 6 . 7
(RTL) Abstração em nível de registradores Descrição em circuitos combinacionais e síncronos Behavioral Descreve o comportamento e não as portas lógicas 6 . 8
is port ( x : in std_logic; y : in std_logic; c_in : in std_logic; s : out std_logic; c_out : out std_logic ); end entity fulladder; architecture rtl of fulladder is begin s <= x xor y xor c_in; c_out <= (x and y) or (c_in and x) or (c_in and y); end architecture rtl; 6 . 11
port ( clk : in std_logic; rst : in std_logic; d : in std_logic; q : out std_logic ); end entity flip_flop; architecture rtl of flip_flop is begin process (rst, clk) begin if rst = '1' then q <= '0'; elsif rising_edge(clk) then q <= d; end if; end process; end architecture rtl; 6 . 12
adder_4_bit is port ( a : in std_logic_vector(3 downto 0); b : in std_logic_vector(3 downto 0); s : out std_logic_vector(3 downto 0); c_out : out std_logic ); end entity adder_4_bit; architecture rtl of adder_4_bit is signal arg_a : unsigned(3 downto 0); signal arg_b : unsigned(3 downto 0); signal sum : unsigned(4 downto 0); begin arg_a <= '0' & unsigned(a); arg_b <= '0' & unsigned(b); sum <= arg_a + arg_b; s <= std_logic_vector(sum(3 downto 0)); c_out <= sum(4); end architecture rtl; 8 . 3
counter_8 is port ( clk : in std_logic; rst : in std_logic; count : out std_logic_vector(7 downto 0) ); end entity counter_8; architecture rtl of counter_8 is signal counter : unsigned(7 downto 0); begin process (rst, clk) begin if rst = '1' then counter <= (others => '0'); elsif rising_edge(clk) then counter <= counter + 1; end if; end process; count <= std_logic_vector(counter); end architecture rtl; 8 . 4