Open SoC Debug

Status update on Open SoC Debug (OSD). Presented at ORConf 2017 in Hebden Bridge, UK.

Transcript

1. Open SoC Debug LibreCores Free and Open Digital Hardware Philipp Wagner @ ORConf 2017 Wei Song, Stefan Wallentowitz
2. Open SoC Debug 2 2017-09-09 What is Open SoC Debug • a spec covering – an extensible debug system architecture – common debug modules – a host-side software programming interface (API) for debug tools • a reference implementation • a collaboration between TUM (OPTiMSoC) and Univ. Cambridge (lowRISC)
3. Open SoC Debug 3 2017-09-09 Run-Control Debug core debug CDM memory access MAM system control SCM UART emulator DEM-UART JTAG (using GLIP) host daemon debug network CPU Core scriptable command line interface gdb server hardware software program or data memory bus clock manager gdb specified and implemented by OSD OSD components available, to be adapted for design host interface HIM third-party IP (freely usable) Image from the OSD Specifcation
4. Open SoC Debug 4 2017-09-09 Trace core debug CDM memory access MAM system control SCM USB 2.0 (using GLIP) host daemon debug network CPU Core 0 scriptable command line interface gdb server hardware software program or data memory clock manager gdb specified and implemented by OSD OSD components available, to be adapted for design host interface HIM third-party IP (freely usable) core trace CTM core debug CDM CPU Core 1 core trace CTM trace viewer custom additions, not part of OSD Image from the OSD Specifcation
5. Open SoC Debug 5 2017-09-09 What’s new? • Large spec rework http://opensocdebug.readthedocs.io/en/latest • Bug fxing in hardware reference implementation • Host software rework in progress – Spotlight: Subnet support
6. Open SoC Debug 6 2017-09-09 Roberto Garrido (via Wikimedia Commons), CC-BY 2.0 Subnets in OSD
7. Open SoC Debug 7 2017-09-09 Situation Today Chip HIM 0 SCM 1 host interface module at address 0 (represents the host) system control module at address 1 provides information about the chip gdbserver trace logger profler host PC
8. Open SoC Debug 8 2017-09-09 Situation Today • clear split host – chip • implementation of multiple tools on host tricky • moving debug processing from host to chip tricky → Goal: Create equal playing feld
9. Open SoC Debug 9 2017-09-09 New: Subnets (or Domains) Chip Subnet 0 subnet controller addr 0.0 subnet controller addr 1.0 subnet controller - tasks of SCM and HIM combined - always at address 0 of the subnet - forwards packets to other subnets - establishes subnet addressing when connecting devices gdbserver addr 1.1 trace logger addr 1.2 profiler addr 1.3 host PC Subnet 1
10. Open SoC Debug 10 2017-09-09 Flexible placement of debug modules Chip Subnet 0 debug processor addr 0.x debug processor addr 0.x subnet controller addr 0 subnet controller addr 1.0 gdbserver addr 1.1 trace logger addr 1.2 profiler addr 1.3 host PC Subnet 1 debug processor addr 1.x debug processor addr 1.x flexible placement of debug processor: either on- chip, or off-chip. flexible placement of debug processor: either on- chip, or off-chip.
11. Open SoC Debug 11 2017-09-09 Extension: Multi-Chip Debugging Chip Subnet 0 subnet controller addr 0.0 subnet controller addr 1.0 gdbserver addr 1.1 trace logger addr 1.2 profiler addr 1.3 host PC Subnet 1 Chip Subnet 2 subnet controller addr 2.0
12. Open SoC Debug 12 2017-09-09 Additional challenges • add and remove debug modules at runtime (esp. for host modules) • dynamic subnet address allocation
13. Open SoC Debug 13 2017-09-09 via Pixbay, CC0 Back to day-to-day business
14. Open SoC Debug 14 2017-09-09 Summary: What to expect in the next year from OSD? • Signifcantly more HW testing • More robust host SW • More advanced debug modules • More projects using Open SoC Debug?
15. me Philipp Wagner mail@philipp-wagner.com www.philipp-wagner.com let's talk! FOSSi Foundation discussion@lists.librecores.org www.fossi-foundation.org gitter.im/librecores/Lobby You can freely remix this presentaton under the terms of the Creatie Commons BY-SA 4.0 license.