Mainstream digital design ● language based ● such a language is called a Hardware Description Language (HDL) ● industry standard HDLs: Verilog, VHDL Question: what makes an HDL special?
Digital hardware system characteristics ● massive amount of concurrent "threads" ● communication through "signals" ● actions triggered by "events" on signals ● deterministic "by construction" ● fine-grained control of data type bit widths Requirement: an HDL must natively support these characteristics
What is an HDL? ● An HDL is an event-driven microthread programming language, with built-in determinism. ● An HDL must also implement a hardware- friendly type system. ● Warning: Many hardware designers don't want to hear that it's all just software programming!
The design of MyHDL Our goal is to design a Python library that supports the following features ● Microthreads ● Events that trigger actions ● Deterministic communication ● Hardware friendly type system
Determinism in an HDL ● separate phases for: value updates computations ● computation order does not matter! ● More info: www.sigasi.com/content/vhdls-crown-jewel
The leaf object of determinism ● the Signal class ● Signals implement value buffering: s = Signal(0) s.next = 5 ● value updates occur automatically by a scheduler (a.k.a. the "simulator") ● if all communication goes through Signals, the model is deterministic
Events ● Events trigger computation actions ● Signals also define events: ■ value changes ■ 0->1 transition (a "posedge") ■ 1->0 transition (a "negedge") ● Commonly used global synchronizing event: the "clock edge" ● Other events exist, e.g. waiting for a delay
Microthread implementation ● Python generator functions to the rescue # z, a, b, sel are Signal objects (outer scope) def mux(): while True: # loop forever yield a, b, sel # wait on a value change if sel: # of a, b, or sel z.next = a else: z.next = b
Using decorators to create generators: @instance ● @instance decorator creates a generator from a generator function @instance # equivalent to mux = mux() def mux(): while True: yield a, b, sel if sel: z.next = a else: z.next = b
The @always decorator ● @always decorator abstracts an outer "while True" loop followed by a "yield" statement @always(a, b, sel) def mux(): if sel: z.next = a else: z.next = b
Combinatorial logic: @always_comb ● @always_comb decorator automatically infers the "sensitivity" to input value changes @always_comb def mux(): if sel: z.next = a else: z.next = b
Decorators are a great tool to create a domain-specific language ● @instance: most general, multiple yield statements. ● @always: single yield statement, abstracts "while True" loop. ● @always_comb: automatically infers combinatorial sensitivity. ● @always_seq: automatically infers the reset functionality for sequential logic. A unique feature of MyHDL!
MyHDL is minimalistic ● only features that are strictly necessary are implemented ● use native Python features as much as possible, e.g.: ○ lists for random access memory (RAM) ○ tuples for read-only memory (ROM) ● a hardware module is modeled by a function that returns generators ● hierarchy is modeled by a submodule "call"
Hardware-friendly type system ● based on integer arithmetic ● fine-grained control of bit width for efficiency A Puzzle: ● given: a in range(0, 8) and b in range(-8, 8) ● calculate c = a + b ● For example: 7 + -2 = ?
7 + -2: The VHDL answer signal a: unsigned(2 downto 0); signal b: signed(3 downto 0); signal c: signed(4 downto 0); ... c <= a + b; Answer: test.vhd:24:10: no function declarations for operator "+": compilation error.
What's wrong with integer arithmetic in Verilog/VHDL ● based on low-level, non-abstract types: signed/unsigned ● mixed expressions are problematic ● Verilog casts everything to unsigned! ● VHDL's strong typing doesn't work well with low-level types
Integer arithmetic in MyHDL ● the Python way: based on good old integers ● the intbv class: "integer with bit vector capabilities" ● specify range for implementation efficiency a = intbv(0, min=0, max=8) b = intbv(0, min=-8, max=8) ● range boundaries reused in value assertions ● slicing & indexing interface to access the bits z.next = a[2:0]
Sidenote: Synthesis ● a "synthesis tool" is a compiler ● it compiles an HDL hardware model into a gate-level implementation ● the entry point of a fully automated back-end ● only a restricted HDL subset is synthesizable: the Register Transfer Level (RTL) ● available from multiple vendors in all price categories (free to $$$) ● Verilog and VHDL only!
Conversion: connecting to standard design flows ● a subset of MyHDL can be automatically converted to Verilog/VHDL ● the convertor maintains the abstraction level ● however, it supports some unique MyHDL features and automates some tedious tasks ● creates readable VHDL/Verilog that integrates seamlessly in the design flow ● the convertible subset is much broader than the synthesizable subset
Conversion example ● MyHDL code: a = Signal(intbv(0, min=0, max=8)) b = Signal(intbv(0, min=-8, max=8)) c = Signal(intbv(0, min=-8, max=15)) c.next = a + b ● Conversion to Verilog: c <= $signed({1'b0, a}) + b; ● Conversion to VHDL: c <= signed(resize(a, 5)) + b; ● The convertor does the casts and resizings, so you don't have to!
MyHDL's strongest point: Verification ● Verification is by far the hardest task in hardware design ● With MyHDL, hardware verification engineers benefit from Python's expressive power and ecosystem ● Test-driven design (TTD) for hardware (with unittest, py.test...) ● The foundation is an event-driven simulator provided by MyHDL
The MyHDL simulator ● input is a (hierarchical) list of generators, that communicate through signals update signal values check which generators become active run active generators in any order
pypy and MyHDL: a dream team ● pypy is an alternative, Python 2.7 compliant Python interpreter ● JIT technology for speed-up ● benchmark simulations run 8 - 20 faster ● within speed range of commercial VHDL/Verilog simulators ● overnight game changer for "free" :-)
MyHDL resources ● myhdl.org has all the info on: ○ Manual & examples ○ Download & installation instructions ○ Newsgroup & mailing list ○ Users, projects & success stories ○ Development ● @MyHDL on twitter ● Development with mercurial on Bitbucket
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