Kouji Matsui - kekyo • NAGOYA city, AICHI pref., JP • Twitter – @kekyo2 / Facebook • ux-spiral corporation • Microsoft Most Valuable Professional VS and DevTech 2015- • Certified Scrum master / Scrum product owner • Center CLR organizer. • .NET/C#/F#/IL/metaprogramming or like… • Bike rider
Agenda •Physical side scales •Logical side scales •Data stream between physicals and logicals •Locality of reference •Anti-locality of reference •Conclusion
Physical side scales The “cache memory” bind at the fixed CPU/Core (Non configurable) The “shared cache memory” bind at the fixed CPU/Core (Non configurable)
Agenda •Physical side scales •Logical side scales •Data stream between physicals and logicals •Locality of reference •Anti-locality of reference •Conclusion
Agenda •Physical side scales •Logical side scales •Data stream between physicals and logicals •Locality of reference •Anti-locality of reference •Conclusion
Agenda •Physical side scales •Logical side scales •Data stream between physicals and logicals •Locality of reference •Anti-locality of reference •Conclusion
Agenda •Physical side scales •Logical side scales •Data stream between physicals and logicals •Locality of reference •Anti-locality of reference •Conclusion
Agenda •Physical side scales •Logical side scales •Data stream between physicals and logicals •Locality of reference •Anti-locality of reference •Conclusion
Conclusion The execution context bounds not THREAD. The code executor is CPU CORE. CPU cores have structuable nested cache system. Cache miss penalty is large. Cache coherency penalty is large. Both I/O systems too. Important cache-related architecture: ◦ Locality of reference ◦ Immutable
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