LLMs in Chip Design

Transcript

1. IEEE International Conference on LLM-Aided Design, 2026 LARGE LANGUAGE MODELS IN CHIP DESIGN Where Transformers Fit in the Chip Design Stack — and where they don’t Manish Pandey, PhD Synopsys, Inc
2. THE DESIGN STACK From Concept to GDSII Architecture & System-Level Design Spec, architectural exploration, performance models, C++/SystemC • Architectural features Logic Domain Closer to design intent What the chip should do. Front-End: RTL Design & Verification RTL, testbenches, assertions, formal & simulation-based verification Architectural choices, algorithms, and functional behavior. Mask Synthesis & Manufacturing Handoff DRC/LVS, DFM, OPC/RET, mask data prep → GDSII • Instruction sets • C++ / SystemC /RTL models • Testbenches and assertions • Delays and timing arcs Back-End: Synthesis, Place & Route Floorplan, placement, CTS, routing, timing / power closure, signoff • Memories and memory hierarchy Electrical/Physical Domain • Physical aspects: layout geometry Closer to silicon • RLC Electrical effects and signal integrity How the chip physically works. Geometry, materials, electrical and thermal behavior. • Timing and power closure • Perhaps the quantum domain
3. THE DIVIDING LINE Where LLMs Land on the Stack Architecture & System-Level Design Spec, architectural exploration, performance models, C++/SystemC Front-End: RTL Design & Verification Logic domain — LLM-native RTL, C++/SystemC, testbenches, assertions, logs and scripts are text. They sit squarely inside the pretraining distribution, and this is where super-human coding ability pays off directly. Frontier models are natively multimodal for text and images RTL, testbenches, assertions, formal & simulation-based verification the representation breaks Back-End: Synthesis, Place & Route Floorplan, placement, CTS, routing, timing / power closure, signoff Mask Synthesis & Manufacturing Handoff DRC/LVS, DFM, OPC/RET, mask data prep → GDSII Electrical/Physical domain — out of distribution Layout geometry, RLC parasitics, delays and waveforms are continuous and spatial. No large paired corpus exists, so an LLM sees them only as text it was never trained on. Dedicated models beat LLMs here. Geometry, parasitics, layouts etc. and have no equivalent paired corpus.
4. A WORD OF CAUTION A word of Caution: Theory vs Practice Even for the front-end — here is a Claude Fable 5 (max effort) generated Linear Temporal Logic (SVA) property, created for Formal Verification: // Prove Credit Manager Drain completes : after entering drain, no new sends, // and all outstanding credit is eventually recovered. property p_drain_completes; @(posedge clk) disable iff (!rst_n) $rose(drain_mode) |-> strong( (!(vld && rdy)) throughout (##[0:$] (credit_cnt == MAX_CREDIT)) ); endproperty a_drain_completes : assert property (p_drain_completes); Looks good in theory. THE SVA specifies an unbounded property (for liveness) that in practice will be hard to converge. Even for front-end problems, domain knowledge and expertise in building and verifying designs is critical for success. The tools we build embody that experience — that is what makes AI actually work in practice.
5. ATTACKING THE SILICON DOMAIN Below the Line: Match the Model to the Data Lower layers do not become tractable by using a bigger LLM. They become tractable three other ways. ▪ Use the right architecture – Graph networks/GNNs on netlists and layouts – CNNs / ViTs for litho and DRC hotspots – RL for placement and routing ▪ Bridge the representation – Electrical/Physical domain has a text surface: reports, logs, SDC, Tcl – The model reasons about the physics, not in it ▪ Wrap, don’t replace – LLM proposes, engine decides – Propose-and-check, as in formal
6. THE PATTERN Value Today: LLM as Orchestrator, Not Solver in Electrical/Physical Domain The model supplies intent, language and iteration. The EDA engines supply truth à Huge productivity boost with tools today! INPUT PROPOSES DECIDES Engineer intent LLM EDA engine “Close timing on this block” · “why did this path fail?” — stated in natural language Plans the flow, writes Tcl and SDC, forms hypotheses, reads reports, decides what to try next STA, DRC / LVS, place & route, simulation and formal — exact, deterministic, signoffgrade reports, violations, timing logs, counter-examples The LLM never owns correctness. Every proposal is checked by an engine that understands the electrical/physical effects, so a wrong guess costs a run — not a chip respin.
7. WHERE THIS LEAVES US Summary ▪ LLMs alone — no ▪ LLMs with tools — yes ▪ Need new models, representations, training data — rich open research area