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EDSAC Museum on FPGA

EDSAC Museum on FPGA

Google Summer of Code 2017 project with FOSSi Foundation and Embecosm. Presentation at ORConf 2017, Hebden Bridge, UK.

149fb2d897e174c90ad39b5b46e417ca?s=128

Hatim Kanchwala

September 10, 2017
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  1. Hatim Kanchwala <hatim@hatimak.me> ORConf 2017, Hebden Bridge, UK Copyright ©

    2017 Hatim Kanchwala. Freely available under a CC-BY-SA license. EDSAC Museum on FPGA Hatim Kanchwala Final Year Undergraduate, Indian Institute of Technology Patna 1
  2. Hatim Kanchwala <hatim@hatimak.me> ORConf 2017, Hebden Bridge, UK Copyright ©

    2017 Hatim Kanchwala. Freely available under a CC-BY-SA license. Agenda -Background on project -EDSAC details -Status of work -Further work 2
  3. Hatim Kanchwala <hatim@hatimak.me> ORConf 2017, Hebden Bridge, UK Copyright ©

    2017 Hatim Kanchwala. Freely available under a CC-BY-SA license. Background on project -Colleague was doing a simulator of the Harwell WITCH in C/C++ back in 2015 -Developed interest in retro-computers so through colleague I proposed to his mentor to do Verilog implementation of WITCH, but they were not so interested at the moment -Come GSoC 2017, FOSSi Foundation offered a project to replicate EDSAC on FPGA -So, under mentorship of Dr Jeremy Bennett and Stefan Wallentowitz, and a good deal of help from Bill Purvis, spent this summer building the replica of EDSAC on a myStorm board 3
  4. Hatim Kanchwala <hatim@hatimak.me> ORConf 2017, Hebden Bridge, UK Copyright ©

    2017 Hatim Kanchwala. Freely available under a CC-BY-SA license. Background on project -Project’s aim is to reimagine the EDSAC on modern hardware to make the historic computer accessible to and reproducible by a new generation of computer architects and engineers 4
  5. Hatim Kanchwala <hatim@hatimak.me> ORConf 2017, Hebden Bridge, UK Copyright ©

    2017 Hatim Kanchwala. Freely available under a CC-BY-SA license. EDSAC Details -Electronic Delay Storage Automatic Calculator - built by Maurice Wilkes and team at University of Cambridge Mathematical Laboratory in 1949, inspiration from ENIAC and EDVAC (EDVAC used delay lines) -Ran at a clock of about 500 KHz, has 18 instructions - arithmetic, logical (just one), branch, shift, round off (Maurice was really proud of these) and print 5
  6. Hatim Kanchwala <hatim@hatimak.me> ORConf 2017, Hebden Bridge, UK Copyright ©

    2017 Hatim Kanchwala. Freely available under a CC-BY-SA license. EDSAC Details -A few terms: -Pulse Interval (p.i.): the duration of one clock pulse = 2 µs (also interchangeably called a bit) -Minor cycle (M/C): the duration of 36 bits (or 36 p.i.) = 72 µs -Major cycle: the duration 16 M/C = 1.15 ms -Numbers represented in binary form, real decimal notation, i.e., -1 ≤ n < 1 for every number n -2’s complement notation for negative numbers 6
  7. Hatim Kanchwala <hatim@hatimak.me> ORConf 2017, Hebden Bridge, UK Copyright ©

    2017 Hatim Kanchwala. Freely available under a CC-BY-SA license. EDSAC Details -Numbers and Orders input by punch tape (in decimal form, translation to binary carried out automatically) -Two types of Number representations: -short numbers: 5 digit decimal numbers equivalent to 18 p.i. (all Orders are 18 p.i. long) = ½ M/C -long numbers: 10 digit decimal numbers equivalent to 36 p.i. = 1 M/C -Mercury delay lines were basic units of memory, 16 M/C in continuous recirculation (1.15 ms) 7
  8. Hatim Kanchwala <hatim@hatimak.me> ORConf 2017, Hebden Bridge, UK Copyright ©

    2017 Hatim Kanchwala. Freely available under a CC-BY-SA license. EDSAC Details -Memory capacity of around 512 long words (≅ 2 KB) spread across 32 mercury delay lines, later upgraded to 1024 long words -“Flip-flops” used to hold bits for around a millisecond or so, resettable monostable -AND gates called “gates”, OR called “adding diodes” and NOT called “reverser” 8
  9. Hatim Kanchwala <hatim@hatimak.me> ORConf 2017, Hebden Bridge, UK Copyright ©

    2017 Hatim Kanchwala. Freely available under a CC-BY-SA license. EDSAC Details 9
  10. Hatim Kanchwala <hatim@hatimak.me> ORConf 2017, Hebden Bridge, UK Copyright ©

    2017 Hatim Kanchwala. Freely available under a CC-BY-SA license. EDSAC Details -At top level, EDSAC can be divided into 5 subsystems: -Computer (ALU in modern terms) -Control section -I/O -Memory -Pulse generators, power supplies, etc. 10
  11. Hatim Kanchwala <hatim@hatimak.me> ORConf 2017, Hebden Bridge, UK Copyright ©

    2017 Hatim Kanchwala. Freely available under a CC-BY-SA license. EDSAC Details 11
  12. Hatim Kanchwala <hatim@hatimak.me> ORConf 2017, Hebden Bridge, UK Copyright ©

    2017 Hatim Kanchwala. Freely available under a CC-BY-SA license. EDSAC Details -At top level, EDSAC can be divided into 5 subsystems: -Computer (ALU in modern terms) -72 bit wide Accumulator (to accommodate full result of a multiplication) -Multiplier and Multiplicand, each 36 bit wide -Accumulator Shifting Units (left/right shifts, multiplication) -Dedicated Complementer unit -Only one logic function, logical AND (called collation) 12
  13. Hatim Kanchwala <hatim@hatimak.me> ORConf 2017, Hebden Bridge, UK Copyright ©

    2017 Hatim Kanchwala. Freely available under a CC-BY-SA license. EDSAC Details 13
  14. Hatim Kanchwala <hatim@hatimak.me> ORConf 2017, Hebden Bridge, UK Copyright ©

    2017 Hatim Kanchwala. Freely available under a CC-BY-SA license. EDSAC Details -At top level, EDSAC can be divided into 5 subsystems: -Computer (ALU in modern terms) -Control section -Two stages of operation: -Stage 1: Order is loaded into Order Tank from Memory (Instruction Fetch in modern terms) -Stage 2: Order is executed and Memory transactions performed (if any) 14
  15. Hatim Kanchwala <hatim@hatimak.me> ORConf 2017, Hebden Bridge, UK Copyright ©

    2017 Hatim Kanchwala. Freely available under a CC-BY-SA license. EDSAC Details -Two stages of operation: -Stage 1: Order is loaded into Order Tank from Memory (Instruction Fetch in modern terms) -Coincidence Unit, Order Flashing Unit and Tank Decoding Units find Order from Memory -Sequence Control Tank provides address of Order to load (Instruction Pointer in modern terms) -Order flows into Order Flashing Unit which sets up flip-flops 15
  16. Hatim Kanchwala <hatim@hatimak.me> ORConf 2017, Hebden Bridge, UK Copyright ©

    2017 Hatim Kanchwala. Freely available under a CC-BY-SA license. EDSAC Details -Two stages of operation: -Stage 1: Order is loaded into Order Tank from Memory (Instruction Fetch in modern terms) -Two stages of order decoding produce a signal signifying the opcode -5 bits in the order signify the opcode/symbol -Order coder generates all control signals for the execution of Order 16
  17. Hatim Kanchwala <hatim@hatimak.me> ORConf 2017, Hebden Bridge, UK Copyright ©

    2017 Hatim Kanchwala. Freely available under a CC-BY-SA license. EDSAC Details -Two stages of operation: -Stage 2: Order is executed and Memory transactions performed (if any) -Coincidence Unit and Tank Decoding Units find Number from Memory -Number flows into Multiplicand Tank into Accumulator I via Distribution Unit and Adder -Execution is performed under the supervision of Computer Control Unit (CCU) and Timing Control and Shifting Unit 17
  18. Hatim Kanchwala <hatim@hatimak.me> ORConf 2017, Hebden Bridge, UK Copyright ©

    2017 Hatim Kanchwala. Freely available under a CC-BY-SA license. EDSAC Details -Two stages of operation: -Stage 2: Order is executed and Memory transactions performed (if any) -Result flows out from Accumulator to Memory via Accumulator Shifting Units 18
  19. Hatim Kanchwala <hatim@hatimak.me> ORConf 2017, Hebden Bridge, UK Copyright ©

    2017 Hatim Kanchwala. Freely available under a CC-BY-SA license. EDSAC Details -At top level, EDSAC can be divided into 5 subsystems: -Computer (ALU in modern terms) -Control section -Two stages of operation -Transfer Unit aligns decimal point of short words by introducing ½ M/C delays (when relevant) -The most complex unit and the source of significant issues 19
  20. Hatim Kanchwala <hatim@hatimak.me> ORConf 2017, Hebden Bridge, UK Copyright ©

    2017 Hatim Kanchwala. Freely available under a CC-BY-SA license. EDSAC Details 20
  21. Hatim Kanchwala <hatim@hatimak.me> ORConf 2017, Hebden Bridge, UK Copyright ©

    2017 Hatim Kanchwala. Freely available under a CC-BY-SA license. EDSAC Details -At top level, EDSAC can be divided into 5 subsystems: -Computer (ALU in modern terms) -Control section -I/O -Punch tape reader, teleprinter -CRT screens displaying register contents and memory bank contents -Initial orders loader, Control panel, Telephone dial 21
  22. Hatim Kanchwala <hatim@hatimak.me> ORConf 2017, Hebden Bridge, UK Copyright ©

    2017 Hatim Kanchwala. Freely available under a CC-BY-SA license. EDSAC Details -At top level, EDSAC can be divided into 5 subsystems: -Computer (ALU in modern terms) -Control section -I/O -Memory -32 Memory Tanks spread over 4 racks 22
  23. Hatim Kanchwala <hatim@hatimak.me> ORConf 2017, Hebden Bridge, UK Copyright ©

    2017 Hatim Kanchwala. Freely available under a CC-BY-SA license. Status of work -Goal was to be as faithful to the original replica as possible - use the original architecture and logic diagrams, signal timing, and run at original speed -EDSAC was operational for around a decade and underwent several upgrades that are not well documented -The Verilog modules for all the subsystems are ready - some of them run on the myStorm board and some of them don’t so it is WIP ;) https://github.com/librecores/gsoc-museum-edsac 23
  24. Hatim Kanchwala <hatim@hatimak.me> ORConf 2017, Hebden Bridge, UK Copyright ©

    2017 Hatim Kanchwala. Freely available under a CC-BY-SA license. Further work -I/O Flavours -Currently replica is only FPGA, need to replicate ancient I/O on modern hardware (remember our project aim?) -Broad idea is to make these I/O peripherals extensible so users can hack any hardware at their disposal and plug-and-play -Assembler -Any more ideas? Yes, gladly welcomed 24
  25. Hatim Kanchwala <hatim@hatimak.me> ORConf 2017, Hebden Bridge, UK Copyright ©

    2017 Hatim Kanchwala. Freely available under a CC-BY-SA license. Acknowledgements -My trip to the UK was made possible by funding from Embecosm and FOSSi Foundation -I would like to thank my mentors for the project - Dr Jeremy Bennett and Stefan Wallentowitz -Huge thanks are due to Bill Purvis, Logic Designer, EDSAC Replica Project -Thanks are due to Prof. Martin Campbell-Kelly (the de facto authority on EDSAC), and Ken Boak and Al Wood (developers of open-source low-cost myStorm) 25
  26. Hatim Kanchwala <hatim@hatimak.me> ORConf 2017, Hebden Bridge, UK Copyright ©

    2017 Hatim Kanchwala. Freely available under a CC-BY-SA license. Me Hatim Kanchwala
 Final Year Undergraduate
 Electrical Engineering
 Indian Institute of Technology Patna hatim@hatimak.me hatim.ee14@iitp.ac.in 
 https://hatimak.me https://twitter.com/ihatimk If you have any interesting projects or opportunities, please drop an email or tweet, would love to hear 26