Interactive Scores Meet Timed Automata

Transcript

1. Interactive Scores Meet Timed Automata Jaime Arias, Myriam Desainte-Catherine and Camilo Rueda LaBRI – Université de Bordeaux GT PoSET, November 2014
2. A Framework for Writing and Interpreting Interactive Scores Composition IS2UPP Verification Property Checking C/C++ Code VHDL/System Verilog Code UPP2C UPP2HDL i-score scenario UPPAAL model Interpretation 0% 90%
3. Composition : i-score Texture Structure Rigid Interval Semi-Flexible Interval Interaction Point OSC Messages Multimedia Processes
4. Edition Simulation Verification Verification : UPPAAL Model Timed CTL
5. Verification : UPPAAL Model t  0 t = 0 eventi! msg := i Modelling an event
6. Verification : UPPAAL Model C send! C starti? skipi? killi? data := 0 C killi? send! data := n t := 0 t  0 t = 0 stopi? send! data := n 1 t := 0 Modelling a multimedia process
7. Verification : UPPAAL Model t := 0 killj? killj? t  0 t = 0 skipi? stopi! initiatei? C C killi! skipk! Modelling a rigid interval / texture
8. Verification : UPPAAL Model initiatei? t := 0 t  0 t = 0 t  1 t = 1 timeouti? skipi? killi? killi? killi? mini! C C skipj! killj! C stopi! killi? timeouti? t = 0 mini! 1 6= 1 1 = 1 Modelling a flexible interval / structure / * with interaction points
9. Verification : UPPAAL Model •  But … we also want to stop the children of a structure. C stopi? killi! skipj? killj? Mixing some events
10. Verification : UPPAAL Model C C C starti? eventi? startj! stopi? skipj! urgent = true urgent = false skipj ! stopi ? stopi? condi( val ) = false condi( val ) = true skip i ? killi? enable := false enable = true enable = false enable := true eventi? Modelling an interaction point
11. Verification : UPPAAL Model •  Also, we need to handle one or more temporal intervals. C mini? counter + + , pass := false skipi? counter + + counter < n counter = n ^ pass = true counter = n ^ pass = false skipj! stopj! killj? Controlling several temporal intervals interactive interval 1 interactive interval 2 merge interactive (1,2) min max min max min max interaction point enabled time
12. Execution : An FPGA
13. Execution : An FPGA Hardware Design Verification Language Verilog and C++ SystemVerilog
14. Execution : An FPGA
15. Execution : An FPGA
17. References [1] R. Trausmuth, C. Dusek, and Y. Orlarey, “Using FAUST for FPGA Programming,” in 9th International Conference on Digital Audio Effects, 2006, pp. 18–20. [2] R. Aviziensis, A. Freed, T. Suzuki, and D. Wessel, “Scalable Connectivity Processor for Computer Music Performance Systems,” in International Computer Music Conference, 2000. [3] J. Echeveste, A. Cont, J.-L. Giavitto, and F. Jacquemard, “Operational semantics of a domain specific language for real time musician–computer interaction,” Discret. Event Dyn. Syst., vol. 23, no. 4, pp. 343–383, Apr. 2013. [4] Y. Jiang, H. Zhang, Z. Li, Y. Deng, X. Song, M. Gu, and J. Sun, “Design and Optimization of Multi-clocked Embedded Systems using Formal Techniques,” IEEE Trans. Ind. Electron., pp. 1–1, 2014. [1] M. Pajic, Z. Jiang, I. Lee, O. Sokolsky, and R. Mangharam, “From Verification to Implementation: A Model Translation Tool and a Pacemaker Case Study,” in Real Time and Embedded Technology and Applications Symposium, 2012, pp. 173–184.