Transactions in Relaxed Memory Architectures

POPL 2018 Talk

Transcript

1. RAFT 1/12 Transactions in Relaxed Memory Architectures Brijesh Dongol Radha Jagadeesan James Riely
2. RAFT 2/12 Transactional Memory Replace locks with transactions Well studied ...
3. RAFT 2/12 Transactional Memory Replace locks with transactions Well studied ... Atomicity = all or nothing
4. RAFT 2/12 Transactional Memory Replace locks with transactions Well studied ... Atomicity = all or nothing Commi eds: What order? Standard serializability: ∃ total order (arbitrary) Strict serializability: ∃ total order respecting real-time order Causal serializability: ∃ partial order respecting causality
5. RAFT 2/12 Transactional Memory Replace locks with transactions Well studied ... Atomicity = all or nothing Commi eds: What order? Standard serializability: ∃ total order (arbitrary) Strict serializability: ∃ total order respecting real-time order Causal serializability: ∃ partial order respecting causality Aborteds: Can a ect client? Yes: Opacity — Aborteds must fit in commi ed order No: TMS1, VWC, ... — Intuition less clear
6. RAFT 2/12 Transactional Memory Replace locks with transactions Well studied ... Atomicity = all or nothing Commi eds: What order? Standard serializability: ∃ total order (arbitrary) Strict serializability: ∃ total order respecting real-time order Causal serializability: ∃ partial order respecting causality Aborteds: Can a ect client? Yes: Opacity — Aborteds must fit in commi ed order No: TMS1, VWC, ... — Intuition less clear How does nontransactional code see transaction? Atomically: Strong isolation As individual operations: Weak isolation
7. RAFT 2/12 Transactional Memory Replace locks with transactions Well studied ... Atomicity = all or nothing Commi eds: What order? Standard serializability: ∃ total order (arbitrary) Strict serializability: ∃ total order respecting real-time order Causal serializability: ∃ partial order respecting causality Aborteds: Can a ect client? Yes: Opacity — Aborteds must fit in commi ed order No: TMS1, VWC, ... — Intuition less clear How does nontransactional code see transaction? Atomically: Strong isolation As individual operations: Weak isolation ... assuming memory is sequentially consistent (SC) What about relaxed memory?
8. RAFT 3/12 Transactional Memory ... Relaxed Atomicity, as before
9. RAFT 3/12 Transactional Memory ... Relaxed Atomicity, as before Order for commi eds? Idea: Use order from underlying memory model
10. RAFT 3/12 Transactional Memory ... Relaxed Atomicity, as before Order for commi eds? Idea: Use order from underlying memory model ⇒ causal serializability ⇐ strict serializability / ⇔ standard serializability, in general Respects causality: us  standard Single total order:  us standard
11. RAFT 3/12 Transactional Memory ... Relaxed Atomicity, as before Order for commi eds? Idea: Use order from underlying memory model ⇒ causal serializability ⇐ strict serializability / ⇔ standard serializability, in general Respects causality: us  standard Single total order:  us standard ⇒ standard serializability, for GHB models, e.g. TSO and ARMv8 Respects causality: us  standard Single total order: us standard In paper: Observational serializability ⇒ causal & standard
12. RAFT 3/12 Transactional Memory ... Relaxed Atomicity, as before Order for commi eds? Idea: Use order from underlying memory model ⇒ causal serializability ⇐ strict serializability / ⇔ standard serializability, in general Respects causality: us  standard Single total order:  us standard ⇒ standard serializability, for GHB models, e.g. TSO and ARMv8 Respects causality: us  standard Single total order: us standard In paper: Observational serializability ⇒ causal & standard Aborteds: Can a ect client? Natural formalization of opacity (Ignoring realtime) New perspective on weaker conditions (TMS1, VWC, ...)
13. RAFT 3/12 Transactional Memory ... Relaxed Atomicity, as before Order for commi eds? Idea: Use order from underlying memory model ⇒ causal serializability ⇐ strict serializability / ⇔ standard serializability, in general Respects causality: us  standard Single total order:  us standard ⇒ standard serializability, for GHB models, e.g. TSO and ARMv8 Respects causality: us  standard Single total order: us standard In paper: Observational serializability ⇒ causal & standard Aborteds: Can a ect client? Natural formalization of opacity (Ignoring realtime) New perspective on weaker conditions (TMS1, VWC, ...) Nontransactional code? Natural formalization of isolated and relaxed
14. RAFT 4/12 Herding Cats! Axiomatic model Alglave, Maranget and Tautschnig (AMT) Unifying framework for TSO, Power, ARMv7, etc
15. RAFT 4/12 Herding Cats! Axiomatic model Alglave, Maranget and Tautschnig (AMT) Unifying framework for TSO, Power, ARMv7, etc Events labelled by action (Rx1, Wx1)
16. RAFT 4/12 Herding Cats! Axiomatic model Alglave, Maranget and Tautschnig (AMT) Unifying framework for TSO, Power, ARMv7, etc Events labelled by action (Rx1, Wx1) Relations over events, including Program generated (ML syntax) Program order Wx1 po − − → Wy1 e.g., x:=1;y:=1
17. RAFT 4/12 Herding Cats! Axiomatic model Alglave, Maranget and Tautschnig (AMT) Unifying framework for TSO, Power, ARMv7, etc Events labelled by action (Rx1, Wx1) Relations over events, including Program generated (ML syntax) Program order Wx1 po − − → Wy1 e.g., x:=1;y:=1 Data dependency Rx1 data − − − → Wy1 e.g., y:=!x Address dependency Rxy addr − − − − → Wy1 e.g., !x:=1 Control dependency Rx1 ctrl − − − → Wy1 e.g., if !x then y:=1
18. RAFT 4/12 Herding Cats! Axiomatic model Alglave, Maranget and Tautschnig (AMT) Unifying framework for TSO, Power, ARMv7, etc Events labelled by action (Rx1, Wx1) Relations over events, including Program generated (ML syntax) Program order Wx1 po − − → Wy1 e.g., x:=1;y:=1 Data dependency Rx1 data − − − → Wy1 e.g., y:=!x Address dependency Rxy addr − − − − → Wy1 e.g., !x:=1 Control dependency Rx1 ctrl − − − → Wy1 e.g., if !x then y:=1 Resolving nondeterminism Reads-from Wx1 rf − → Rx1 e.g., x:=1 y:=!x
19. RAFT 4/12 Herding Cats! Axiomatic model Alglave, Maranget and Tautschnig (AMT) Unifying framework for TSO, Power, ARMv7, etc Events labelled by action (Rx1, Wx1) Relations over events, including Program generated (ML syntax) Program order Wx1 po − − → Wy1 e.g., x:=1;y:=1 Data dependency Rx1 data − − − → Wy1 e.g., y:=!x Address dependency Rxy addr − − − − → Wy1 e.g., !x:=1 Control dependency Rx1 ctrl − − − → Wy1 e.g., if !x then y:=1 Resolving nondeterminism Reads-from Wx1 rf − → Rx1 e.g., x:=1 y:=!x From-read Rx0 fr − → Wx1 e.g., x:=1 y:=!x
20. RAFT 4/12 Herding Cats! Axiomatic model Alglave, Maranget and Tautschnig (AMT) Unifying framework for TSO, Power, ARMv7, etc Events labelled by action (Rx1, Wx1) Relations over events, including Program generated (ML syntax) Program order Wx1 po − − → Wy1 e.g., x:=1;y:=1 Data dependency Rx1 data − − − → Wy1 e.g., y:=!x Address dependency Rxy addr − − − − → Wy1 e.g., !x:=1 Control dependency Rx1 ctrl − − − → Wy1 e.g., if !x then y:=1 Resolving nondeterminism Reads-from Wx1 rf − → Rx1 e.g., x:=1 y:=!x From-read Rx0 fr − → Wx1 e.g., x:=1 y:=!x Coherence Wx1 co − − → Wx2 e.g., x:=1 x:=2
21. RAFT 4/12 Herding Cats! Axiomatic model Alglave, Maranget and Tautschnig (AMT) Unifying framework for TSO, Power, ARMv7, etc Events labelled by action (Rx1, Wx1) Relations over events, including Program generated (ML syntax) Program order Wx1 po − − → Wy1 e.g., x:=1;y:=1 Data dependency Rx1 data − − − → Wy1 e.g., y:=!x Address dependency Rxy addr − − − − → Wy1 e.g., !x:=1 Control dependency Rx1 ctrl − − − → Wy1 e.g., if !x then y:=1 Resolving nondeterminism Reads-from Wx1 rf − → Rx1 e.g., x:=1 y:=!x From-read Rx0 fr − → Wx1 e.g., x:=1 y:=!x Coherence Wx1 co − − → Wx2 e.g., x:=1 x:=2 Architecture generated Preserved program order For SC: ppo = po For TSO: ppo = po \ WR
22. RAFT 5/12 Herding Cats! Axiomatic model Alglave, Maranget and Tautschnig (AMT) Unifying framework for TSO, Power, ARMv7, etc Execution is valid if it satisfies certain acyclicity requirements
23. RAFT 5/12 Herding Cats! Axiomatic model Alglave, Maranget and Tautschnig (AMT) Unifying framework for TSO, Power, ARMv7, etc Execution is valid if it satisfies certain acyclicity requirements Load bu ering example: Forbidden under SC, where ppo = po Initially: x=y=0 Thread 1: x:=1; read y; Thread 2: y:=1; read x; init Wx1 Ry0 Wy1 Rx0 co co rf rf ppo ppo fr fr
24. RAFT 5/12 Herding Cats! Axiomatic model Alglave, Maranget and Tautschnig (AMT) Unifying framework for TSO, Power, ARMv7, etc Execution is valid if it satisfies certain acyclicity requirements Load bu ering example: Forbidden under SC, where ppo = po Initially: x=y=0 Thread 1: x:=1; read y; Thread 2: y:=1; read x; init Wx1 Ry0 Wy1 Rx0 co co rf rf po po fr fr Allowed under TSO, where ppo = po \ WR
25. RAFT 5/12 Herding Cats! Axiomatic model Alglave, Maranget and Tautschnig (AMT) Unifying framework for TSO, Power, ARMv7, etc Execution is valid if it satisfies certain acyclicity requirements Load bu ering example: Forbidden under SC, where ppo = po Initially: x=y=0 Thread 1: x:=1;FF;read y; Thread 2: y:=1;FF;read x; init Wx1 Ry0 Wy1 Rx0 co co rf rf hb hb fr fr Allowed under TSO, where ppo = po \ WR To get a cycle under TSO, add fences
26. RAFT 6/12 A simple idea Load bu ering example: Allowed under TSO Initially: x=y=0 Thread 1: x:=1;read y Thread 2: y:=1;read x init Wx1 Ry0 Wy1 Rx0 po po co co rf rf fr fr
27. RAFT 6/12 A simple idea Load bu ering example: Allowed under TSO, without atomics Initially: x=y=0 Thread 1: atomic{x:=1;read y} Thread 2: atomic{y:=1;read x} init Wx1 Ry0 Wy1 Rx0 po po co co rf rf fr fr Transaction shown as boxes
28. RAFT 6/12 A simple idea Load bu ering example: Allowed under TSO, without atomics Initially: x=y=0 Thread 1: atomic{x:=1;read y} Thread 2: atomic{y:=1;read x} init Wx1 Ry0 Wy1 Rx0 po po fr fr fr fr co co co co rf rf rf rf Transaction shown as boxes To achieve atomicity, li relations across transactions Independent discovery by Chong, Sorensen and Wickerson
29. RAFT 6/12 A simple idea Load bu ering example: Allowed under TSO, without atomics Initially: x=y=0 Thread 1: atomic{x:=1;read y} Thread 2: atomic{y:=1;read x} init Wx1 Ry0 Wy1 Rx0 po po fr fr fr fr co co co co rf rf rf rf Transaction shown as boxes To achieve atomicity, li relations across transactions Independent discovery by Chong, Sorensen and Wickerson Not AMT valid: Cycle appears between the reads
30. RAFT 6/12 A simple idea Load bu ering example: Allowed under TSO, without atomics Initially: x=y=0 Thread 1: atomic{x:=1;read y} Thread 2: atomic{y:=1;read x} init Wx1 Ry0 Wy1 Rx0 po po fr fr fr fr co co co co rf rf rf rf Transaction shown as boxes To achieve atomicity, li relations across transactions Independent discovery by Chong, Sorensen and Wickerson Not AMT valid: Cycle appears between the reads Consequences: AMT valid ⇒ acyclicity ⇒ Causal serializability
31. RAFT 6/12 A simple idea Load bu ering example: Allowed under TSO, without atomics Initially: x=y=0 Thread 1: atomic{x:=1;read y} Thread 2: atomic{y:=1;read x} init Wx1 Ry0 Wy1 Rx0 po po fr fr fr fr co co co co rf rf rf rf Transaction shown as boxes To achieve atomicity, li relations across transactions Independent discovery by Chong, Sorensen and Wickerson Not AMT valid: Cycle appears between the reads Consequences: AMT valid ⇒ acyclicity ⇒ Causal serializability Ignores real time
32. RAFT 6/12 A simple idea Load bu ering example: Allowed under TSO, without atomics Initially: x=y=0 Thread 1: atomic{x:=1;read y} Thread 2: atomic{y:=1;read x} init Wx1 Ry0 Wy1 Rx0 po po fr fr fr fr co co co co rf rf rf rf Transaction shown as boxes To achieve atomicity, li relations across transactions Independent discovery by Chong, Sorensen and Wickerson Not AMT valid: Cycle appears between the reads Consequences: AMT valid ⇒ acyclicity ⇒ Causal serializability Ignores real time Erase empty transactions, singletons
33. RAFT 6/12 A simple idea Load bu ering example: Allowed under TSO, without atomics Initially: x=y=0 Thread 1: atomic{x:=1;read y} Thread 2: atomic{y:=1;read x} init Wx1 Ry0 Wy1 Rx0 po po fr fr fr fr co co co co rf rf rf rf Transaction shown as boxes To achieve atomicity, li relations across transactions Independent discovery by Chong, Sorensen and Wickerson Not AMT valid: Cycle appears between the reads Consequences: AMT valid ⇒ acyclicity ⇒ Causal serializability Ignores real time Erase empty transactions, singletons Li includes nontransactional ⇒ Strong isolation
34. RAFT 7/12 Some goals Nested transactions Weak isolation (Example under TSO) Rx1 Wx1 Wx2 po rf fr  strong weak Abort models (Example under TSO) init Wx2 Rx0 Wy1 Rx2 Ry0 rf fr fr rf rf  opaque non-opaque
35. RAFT 8/12 Definition Execution is correct if AMT valid with li ed relations e li (o) − − − − → d when either 1. e o − → d 2. or e o − → d for some e ∈ trans(e), d trans(e) 3. or symmetrically for d
36. RAFT 8/12 Definition Execution is correct if AMT valid with li ed relations e li (o) − − − − → d when either 1. e o − → d 2. or e o − → d for some e ∈ descend(e), d descend(e) 3. or symmetrically for d Refinements: Nesting: e in same or sub-transaction of e
37. RAFT 8/12 Definition Execution is correct if AMT valid with li ed relations e li (o) − − − − → d when either 1. e o − → d 2. or e o − → d for some e ∈ descend(e), d descend(e), e ∈ StrongIsolated 3. or symmetrically for d Refinements: Nesting: e in same or sub-transaction of e Weak isolated not seen atomically
38. RAFT 8/12 Definition Execution is correct if AMT valid with li ed relations e li (o) − − − − → d when either 1. e o − → d 2. or e o − → d for some e ∈ descend(e), d descend(e), either e ∈ StrongIsolated or d ∈ Transactional 3. or symmetrically for d Refinements: Nesting: e in same or sub-transaction of e Weak isolated not seen atomically, except by transactions
39. RAFT 8/12 Definition Execution is correct if AMT valid with li ed relations e li (o) − − − − → d when either 1. e o − → d 2. or e o − → d for some e ∈ descend(e), d descend(e), either e ∈ StrongIsolated or d ∈ Transactional 3. or symmetrically for d Refinements: Nesting: e in same or sub-transaction of e Weak isolated not seen atomically, except by transactions Opacity: aborteds ordered w.r.t. commi eds ⇒ No changed to li
40. RAFT 8/12 Definition Execution is correct if AMT valid with li ed relations and ∀d ∈ Aborted.∀e ∈ E. d − − − − → e implies e ∈ Aborted e li (o) − − − − → d when either 1. e o − → d 2. or e o − → d for some e ∈ descend(e), d descend(e), either e ∈ StrongIsolated or d ∈ Transactional 3. or symmetrically for d Refinements: Nesting: e in same or sub-transaction of e Weak isolated not seen atomically, except by transactions Opacity: aborteds ordered w.r.t. commi eds ⇒ No changed to li Aborteds only a ect aborteds
41. RAFT 8/12 Definition Execution is correct if AMT valid with li ed relations and ∀d ∈ Aborted.∀e ∈ E. d causal − − − − → e implies e ∈ Aborted e li (o) − − − − → d when either 1. e o − → d 2. or e o − → d for some e ∈ descend(e), d descend(e), either e ∈ StrongIsolated or d ∈ Transactional 3. or symmetrically for d Refinements: Nesting: e in same or sub-transaction of e Weak isolated not seen atomically, except by transactions Opacity: aborteds ordered w.r.t. commi eds ⇒ No changed to li Aborteds only a ect aborteds: causal = rf ∪ data ∪ addr ∪ · · ·
42. RAFT 8/12 Definition Execution is correct if AMT valid with li ed relations and ∀d ∈ Aborted.∀e ∈ E. d causal − − − − → e implies e ∈ Aborted e li (o) − − − − → d when either 1. e o − → d 2. or e o − → d for some e ∈ descend(e), d descend(e), either e ∈ StrongIsolated or d ∈ Transactional 3. or symmetrically for d Refinements: Nesting: e in same or sub-transaction of e Weak isolated not seen atomically, except by transactions Opacity: aborteds ordered w.r.t. commi eds ⇒ No changed to li Aborteds only a ect aborteds: causal = rf ∪ data ∪ addr ∪ · · · Consequences: Causal serializability, No real time, Singletons
43. RAFT 8/12 Definition Execution is correct if AMT valid with li ed relations and ∀d ∈ Aborted.∀e ∈ E. d causal − − − − → e implies e ∈ Aborted e li (o) − − − − → d when either 1. e o − → d 2. or e o − → d for some e ∈ descend(e), d descend(e), either e ∈ StrongIsolated or d ∈ Transactional 3. or symmetrically for d Refinements: Nesting: e in same or sub-transaction of e Weak isolated not seen atomically, except by transactions Opacity: aborteds ordered w.r.t. commi eds ⇒ No changed to li Aborteds only a ect aborteds: causal = rf ∪ data ∪ addr ∪ · · · Consequences: Causal serializability, No real time, Singletons What about standard serializability?
44. RAFT 9/12 Standard Serializability? Independent Reads of Independent Writes (IRIW) Forbidden for Multi-copy atomic, e.g. SC, TSO, ARMv8 init Wx1 Wy1 Rx1 Ry0 Ry1 Rx0 co co addr addr rf rf fr fr
45. RAFT 9/12 Standard Serializability? Independent Reads of Independent Writes (IRIW) Forbidden for Multi-copy atomic, e.g. SC, TSO, ARMv8 init Wx1 Wy1 Rx1 Ry0 Ry1 Rx0 co co addr addr rf rf fr fr Allowed under ARMv7: Writes seen in di erent orders
46. RAFT 9/12 Standard Serializability? Independent Reads of Independent Writes (IRIW) Forbidden for Multi-copy atomic, e.g. SC, TSO, ARMv8 init Wx1 Wy1 Rx1 Ry0 Ry1 Rx0 co co addr addr rf rf fr fr Allowed under ARMv7: Writes seen in di erent orders With transactions: causal serializable  serializable Li / ⇒ Standard serializability, in general
47. RAFT 9/12 Standard Serializability? Independent Reads of Independent Writes (IRIW) Forbidden for Multi-copy atomic, e.g. SC, TSO, ARMv8 init Wx1 Wy1 Rx1 Ry0 Ry1 Rx0 co co addr addr rf rf fr fr Allowed under ARMv7: Writes seen in di erent orders With transactions: causal serializable  serializable Li / ⇒ Standard serializability, in general Li ⇒ Standard serializability, for multi-copy atomic Formalized using Global Happens Before [Alglave 2010]
48. RAFT 10/12 NonOpaque Aborts Forbidden if all commit (Example under TSO) init Wx2 Rx0 Wy1 Rx2 Ry0 rf fr fr rf rf
49. RAFT 10/12 NonOpaque Aborts Forbidden if all commit (Example under TSO) init Wx2 Rx0 Wy1 Rx2 Ry0 rf fr fr rf rf What if bo om transaction aborts?
50. RAFT 10/12 NonOpaque Aborts Forbidden if all commit (Example under TSO) init Wx2 Rx0 Wy1 Rx2 Ry0 rf fr fr rf rf What if bo om transaction aborts? Forbidden under opacity: Aborteds ordered w.r.t. commi eds Allowed under weaker conditions, e.g. VWC (and possibly TMS1)
51. RAFT 10/12 NonOpaque Aborts Forbidden if all commit (Example under TSO) init Wx2 Rx0 Wy1 Rx2 Ry0 rf fr fr rf rf What if bo om transaction aborts? Forbidden under opacity: Aborteds ordered w.r.t. commi eds Allowed under weaker conditions, e.g. VWC (and possibly TMS1) Our solution: Check commi eds and opaques together, ignoring non-opaques
52. RAFT 10/12 NonOpaque Aborts Forbidden if all commit (Example under TSO) init Wx2 Rx0 Wy1 Rx2 Ry0 rf fr fr rf rf What if bo om transaction aborts? Forbidden under opacity: Aborteds ordered w.r.t. commi eds Allowed under weaker conditions, e.g. VWC (and possibly TMS1) Our solution: Check commi eds and opaques together, ignoring non-opaques Check each non-opaque w.r.t. its causal history
53. RAFT 10/12 NonOpaque Aborts Forbidden if all commit (Example under TSO) init Wx2 Rx0 Wy1 Rx2 Ry0 rf fr fr rf rf What if bo om transaction aborts? Forbidden under opacity: Aborteds ordered w.r.t. commi eds Allowed under weaker conditions, e.g. VWC (and possibly TMS1) Our solution: Check commi eds and opaques together, ignoring non-opaques Check each non-opaque w.r.t. its causal history New formal footing for weaker conditions, e.g. VWC and TMS1
54. RAFT 11/12 In the paper Non-Opaques: Comparison with VWC and TMS1
55. RAFT 11/12 In the paper Non-Opaques: Comparison with VWC and TMS1 Automaton to check violations of Global Happens Before Used to prove li ⇒ total order on transactions (for GHB)
56. RAFT 11/12 In the paper Non-Opaques: Comparison with VWC and TMS1 Automaton to check violations of Global Happens Before Used to prove li ⇒ total order on transactions (for GHB) Formalized in Memalloy [Wickerson, et al 2017] TSO, Power and ARMv8 using non-opaque aborts Compared to HW transactions (≤ 5 events)
57. RAFT 11/12 In the paper Non-Opaques: Comparison with VWC and TMS1 Automaton to check violations of Global Happens Before Used to prove li ⇒ total order on transactions (for GHB) Formalized in Memalloy [Wickerson, et al 2017] TSO, Power and ARMv8 using non-opaque aborts Compared to HW transactions (≤ 5 events) HW hides aborted from di erent aborted HW allows We allow
58. RAFT 11/12 In the paper Non-Opaques: Comparison with VWC and TMS1 Automaton to check violations of Global Happens Before Used to prove li ⇒ total order on transactions (for GHB) Formalized in Memalloy [Wickerson, et al 2017] TSO, Power and ARMv8 using non-opaque aborts Compared to HW transactions (≤ 5 events) HW hides aborted from di erent aborted Otherwise, our model strictly more expressive HW enforces coherence with aborted HW places fences before/a er each transaction HW allows We allow We allow We allow
59. RAFT 12/12 Inspiration What do High-Level Memory Models Mean for Transactions? Grossman, Manson and Pugh, 2006 Transactions As the Foundation of a Memory Consistency Model Dalessandro, Sco and Spear, 2010
60. RAFT 12/12 Inspiration What do High-Level Memory Models Mean for Transactions? Grossman, Manson and Pugh, 2006 Transactions As the Foundation of a Memory Consistency Model Dalessandro, Sco and Spear, 2010 A Shared Memory Poetics Alglave, 2010 Herding Cats: Modeling, Simulation, Testing, and Data Mining ... Alglave, Maranget and Tautschnig, 2014
61. RAFT 12/12 Inspiration What do High-Level Memory Models Mean for Transactions? Grossman, Manson and Pugh, 2006 Transactions As the Foundation of a Memory Consistency Model Dalessandro, Sco and Spear, 2010 A Shared Memory Poetics Alglave, 2010 Herding Cats: Modeling, Simulation, Testing, and Data Mining ... Alglave, Maranget and Tautschnig, 2014 Automatically comparing memory consistency models, Wickerson, Ba y, Sorensen and Constantinides, 2017 The Semantics of Transactions ...in x86, Power, ARMv8, and C++ Chong, Sorensen and Wickerson, 2017
62. RAFT 12/12 Inspiration What do High-Level Memory Models Mean for Transactions? Grossman, Manson and Pugh, 2006 Transactions As the Foundation of a Memory Consistency Model Dalessandro, Sco and Spear, 2010 A Shared Memory Poetics Alglave, 2010 Herding Cats: Modeling, Simulation, Testing, and Data Mining ... Alglave, Maranget and Tautschnig, 2014 Automatically comparing memory consistency models, Wickerson, Ba y, Sorensen and Constantinides, 2017 The Semantics of Transactions ...in x86, Power, ARMv8, and C++ Chong, Sorensen and Wickerson, 2017 Our contribution: High-level view of low-level model