21st ACRi Webinar - Univ of Tokyo Presentation Slide (Shinya Takamaeda)

21st ACRi Webinar - Univ of Tokyo Presentation Slide (Shinya Takamaeda)

Transcript

1. %"* ͳͥAI EngineͷݚڀΛ͢Δͷ͔ʁ ౦ژେֶ/ཧݚAIP ߴલా ৳໵ ౦ژେֶ େ໺ า࣮ 2025೥12݄2೔ 17:30-19:00 ୈ21ճACRi΢ΣϏφʔ: AI EngineΛ࢖ͬͯΈΑ͏
2. %"* ౦ژେֶ
   େֶӃ৘ใཧ޻ֶܥݚڀՊ
   ίϯϐϡʔλՊֶઐ߈ ߴલాݚڀࣨ
   CASYS (Computer Architecture and Systems Lab.) JA: https://sites.google.com/view/casys-ja/ EN: https://sites.google.com/view/casys/ ίϯϐϡʔλ ΞʔΩςΫνϟ • ϓϩηοαΞʔΩςΫνϟ • ϝϞϦγεςϜ • υϝΠϯಛԽΞʔΩςΫνϟ • FPGAγεςϜ • ηΩϡΞϓϩηοα (TEE) • ϝϞϦ಺ܭࢉ (CIM) • ৽حσόΠεΛ༻͍ͨ ίϯϐϡʔλ 2 ϋʔυ΢ΣΞઃܭٕज़ • ߴҐ߹੒ίϯύΠϥ • ΞϧΰϦζϜ/ϋʔυ΢ΣΞ ڠௐઃܭ ػցֶशγεςϜ • ෼ࢄػցֶश • ࿈߹ֶश (Federated Learning) • LLMਪ࿦/αʔϏϯάγεςϜ • AI/LLMνοϓ
3. %"* ͳͥʢߴલాݚͰʣAI EngineͷݚڀΛ͢Δͷ͔ʁ ࠓ೔ͷίϯϐϡʔλ͸σʔλͷʮಡΈॻ͖ʯʹଟ͘ͷΤωϧΪʔΛফඅ͍ͯ͠Δ l খ͞ͳϝϞϦؒͰσʔλΛड͚౉͢Spatial Architecture͸ిྗޮ཰͕ྑ͍͸ͣ →AI Engine͸खʹೖΓ΍͍͢Spatial Architectureʂ 3 [Vivienne Sze, NeurIPS 2019] [Mark Horowitz, ISSCC 2014]
4. %"* ͳͥʢߴલాݚͰʣAI EngineͷݚڀΛ͢Δͷ͔ʁ ࠓ೔ͷίϯϐϡʔλ͸σʔλͷʮಡΈॻ͖ʯʹଟ͘ͷΤωϧΪʔΛফඅ͍ͯ͠Δ l খ͞ͳϝϞϦؒͰσʔλΛड͚౉͢Spatial Architecture͸ిྗޮ཰͕ྑ͍͸ͣ →AI Engine͸खʹೖΓ΍͍͢Spatial Architectureʂ 4 [Vivienne Sze, NeurIPS 2019] [Mark Horowitz, ISSCC 2014] ͱ͍͏ͷ͸ݐલ
5. %"* ࡾͭࢠͷࠢඦ·Ͱʁ 2008೥4݄ʙ2014೥3݄ʢֶ෦ɺम࢜՝ఔɺത࢜՝ఔʣͷݚڀςʔϚ: ϝχʔίΞCPUͷϓϩτλΠϐϯάͷͨΊͷϚϧνFPGAγεςϜ 5
6. %"* ࡾͭࢠͷࠢඦ·Ͱʁ 2008೥4݄ʙ2014೥3݄ʢֶ෦ɺम࢜՝ఔɺത࢜՝ఔʣͷݚڀςʔϚ: ϝχʔίΞCPUͷϓϩτλΠϐϯάͷͨΊͷϚϧνFPGAγεςϜ 6 ScalableCore System[takamaeda+, ACM CAN’11][takamaeda+, ARC’12] n An FPGA-node cluster for Many-core Simulation DRAM Controller Power DC5V FPGA SRAM Power FPGA SRAM FPGA SRAM FPGA SRAM FPGA SRAM FPGA SRAM FPGA SRAM FPGA SRAM FPGA SRAM FPGA SRAM FPGA SRAM FPGA SRAM FPGA SRAM FPGA SRAM FPGA SRAM FPGA SRAM ScalableCore Unit (Processor Core) Host USB-Serial USB FPGA DRAM FPGA DRAM FPGA DRAM FPGA DRAM Memory Unit (Off-chip Memory) Local Memory DMAC Core R System Functions Target Core ScalableCore System Target Many-core Mapping to Multiple FPGAs 8 Shinya Takamaeda-Yamazaki, et al. : ScalableCore System: A Scalable Many-core Simulator by Employing Over 100 FPGAs, International Symposium on Applied Reconfigurable Computing (ARC 2012) (March 2012). Shinya Takamaeda-Yamazaki, et al.: An FPGA-based Scalable Simulation Accelerator for Tile Architectures, ACM COMPUTER ARCHITECTURE NEWS, Vol.39, No.4 (2011) ScalableCore System of 100 FPGA Nodes Memory Unit (for DRAM Controller): FPGA+DRAM board 46.7cm 60.0cm Local Memory DMAC Core R System Functions ScalableCore Unit (for Processor Core): FPGA+SRAM board 9
7. %"* AI Engine ≒ ͋ͷࠒඳ͍ͨϝχʔίΞCPU 7 Memory AMD XDNAä ΞʔΩςΫνϟ https://www.amd.com/ja/technologies/xdna.html ≒
8. %"* AI Engine ≒ ͋ͷࠒඳ͍ͨϝχʔίΞCPU 8 Memory AMD XDNAä ΞʔΩςΫνϟ https://www.amd.com/ja/technologies/xdna.html ≒ ྑ͍ϋʔυ΢ΣΞΛ׆༻͢Δ ΞϧΰϦζϜɺϓϩάϥϛϯάϞσϧɺ ίϯύΠϥ౳ͷιϑτ΢ΣΞٕज़͕ඞཁ