lowRISC talk (ETH Zurich)

lowRISC talk given at ETH Zurich by Robert Mullins, November 2014

Transcript

1. The lowRISC project Robert Mullins Computer Laboratory
2. “Subject: Redo BBC Micro”
3. “Subject: Development of an open-source SoC” • Why create an open source SoC? – Teaching and Research – Demand from Industry – Startups and innovation (be disruptive!) – Open-source community – Why now?
4. How? • Not-for-profit company (lowRISC), building TAB • Grow Cambridge team to seed project • Engage early and build a community • Share ideas, SW and RTL early and often • Permissive open source license • Multiple volume silicon runs • Expose interesting new features (new toys!)
5. Approach to design • Aim for simplicity – Minimal set of hardware features/primitives • Free from commercial influences and release cycles – Cores are free and customisable (one ISA) – Aim to maximise functionality (no product range!) – Clean sheet design
6. RISC-V • RISC-V ISA from Berkeley – Aim to create open ISA standard for industry – Explicitly designed to be extensible – Simple base integer ISA (~40 instructions) – 32-bit, 64-bit, 128-bit (!) variants • Simple SoC generator available (incl. cores) • Open source HDL - Chisel
8. Tagged Memory • Associate tags (metadata) with each memory location • Initial motivation is prevention of control-flow hijacking attacks (still a major attack surface) • Provide protection for code-pointers – i.e. set tag bit = read only – One subtlety is need to check tag is present upon load (prior to branch) in case of use-after- free
9. Tagged Memory • Low-overhead implementation • Tag bits copied to L1/L2 + on-chip tag cache • Exploring 2-bit tags (~3% storage overhead) • ISA support • Ability to use tags simply as data • Configurable policy triggers interrupt
10. Tagged Memory – beyond security • Infinite memory watchpoints • Better version of traditional canaries • Garbage collection • Accelerate debug tools (e.g. Google *Sanitizer) – e.g. use-after-free detection • Per-word locks, full/empty bits for synchronization • Mark valid targets of indirect branches
12. Minion Cores • Motivation – Soft peripherals – I/O preprocessing/filtering, wake-up main cores – Off-load fine-grain tasks, e.g. security policies • Debugging, performance monitoring, …. – Off-load tasks from main cores
13. Minion Cores • Support for soft peripherals is not a new idea – CDC6600, TI PRUs, Ubicom IP3000, XMOS – NXP LPC4370 (M4 + 2xMO for peripherals)
14. Minion Cores - architecture • Predictable timing • ISA support for precise timing • I/O 'shim' – Logic to aid shift in/out, parallel load, buffer data, provide clocks, assign pins to minions.. • Low-latency path between main cores and minions – May carry cache misses, branch mispredicts..
15. Roadmap • Q1 2015 - Tagged memory (FPGA) • Q2 2015 – Minion cores (FPGA) • End 2015 – Dual-core test-chip, with integrated memory PHY, minions • First volume run 2016/17
16. Final thoughts... • Very keen to receive input at this stage, explore possible collaborations etc. • www.lowrisc.org • Announcement and discussion lists • Questions, ideas? Robert.Mullins@cl.cam.ac.uk