TN Chan

Heterogeneous Multi-Processing Big Bang

Transcript

1. Heterogeneous Multi- Processing Big Bang MW14 Auckland TN Chan tn@compucon.co.nz Contributors: Dr A Ensor, Prof J Bancroft, Dr R Nicolescu, Dr R Hasan
2. NZ on Stage • SKA Central Position o CSP Survey PIP o NZ Government recognition • HPC COE o 1 of several projects initiated o Started with 5 core members o 20 process milestones o Slightly in-synch with SKA CSP design Advisors, contributors, members wanted
3. Background • EU FP7 SAVE o 2013-09 for 3 years • Hardware for Application? o Many Core, GPU, FPGA, … o Performance, Energy, FFP/TCO • JIT Dynamic allocations o Memory Coherence (HSA)
4. Real Performance • Xilinx FPGA Z7020 relative to dual ARM cores • Linux, LINQ, C# RT, FPGA templates • Microsoft Research LINQits: Big Data on Little Clients Black Scholes K- means 25xP 18xE 10xP 9xE
5. Real Hardware • HW o ARM o FPGA o MC • (routers) • (64) o 5W • SW o C & OCL o Linux • Sampling o Adapteva Epiphany Parallella
6. Real Software • Smart Phone and Tablet shows us the way o Example taken from Microchip IDE o Multi-vendors • RTOS • TCP/IP drivers • SSL drivers • In theory o Copy to HPC environments o Scale up to global movements o Instil open source and access Application Runtime IDE
7. Summary • Heterogeneous Multiprocessing is realistic o Performance gain o Hardware o Software o People • NZ on Stage o Advisors, contributors, and developers wanted o Passion and Talent based