Cache miss paper

36 Cache Miss Paper Simulation • 8B cache, 2B blocks
à 4 sets • Offset: 1 bit. Index: 2 bits • What happens for each request? Address Tag Index Offset Set 0 Set 1 Set 2 Set3 Result C invalid 0 0 1 E 8 3 8 0 8 4 6

40 Cache Miss Paper Simulation • 8B cache, 2B blocks
à 4 sets Address Tag Index Offset Set 0 Set 1 Set 2 Set3 Result C 1 2 0 invalid 0 0 1 Miss E 1 3 0 invalid 0 1 1 Hit 8 1 0 0 invalid 0 1 1 Miss 3 0 1 1 1 0 1 1 Hit 8 1 0 0 1 0 1 1 Hit 0 0 0 0 1 0 1 1 Miss 8 1 0 0 0 0 1 1 Miss 4 0 2 0 1 0 1 1 Miss 6 0 3 0 1 0 0 1 Miss • Offset: 1 bit. Index: 2 bits • What happens for each request?

46 Cache Miss Paper Simulation (4B instead 2B blocks) •
8B cache, 4B blocks à 2 sets Address Tag Index Offset Set 0 Set 1 Result C invalid 0 Miss E Hit 8 Miss 3 Miss 8 Miss 0 Miss 8 Miss 4 Miss 6 Hit • What happens for each request?

47 Cache Miss Paper Simulation (4B instead 2B blocks) •
8B cache, 4B blocks à 2 sets Address Tag Index Offset Set 0 Set 1 Result C 1 1 0 invalid 0 Miss E 1 1 2 invalid 1 Hit 8 1 0 0 invalid 1 Miss 3 0 0 3 1 1 Miss 8 1 0 0 0 1 Miss 0 0 0 0 1 1 Miss 8 1 0 0 0 1 Miss 4 0 1 0 1 1 Miss 6 0 1 2 1 0 Hit • Offset: 2 bits. Index: 1 bit • 8,3: new conflicts (fewer sets) • 4,6: spatial locality

52 Cache Behavior in 2-ways Set # Way 0 Way
1 V Tag Data V Tag Data 0 0 000 00 00 00 00 0 000 00 00 00 00 1 0 000 00 00 00 00 0 000 00 00 00 00 2 0 000 00 00 00 00 0 000 00 00 00 00 3 0 000 00 00 00 00 0 000 00 00 00 00 Cache: 4 sets, 2 ways, 4B blocks

53 Cache Behavior 2-ways Set # Way 0 Way 1
V Tag Data V Tag Data 0 0 000 00 00 00 00 0 000 00 00 00 00 1 0 000 00 00 00 00 0 000 00 00 00 00 2 0 000 00 00 00 00 0 000 00 00 00 00 3 0 000 00 00 00 00 0 000 00 00 00 00 Access address 0x1234 = 0001 0010 0011 0100 Offset = 0 Index = 1 Tag = 291 Miss. Request from next level. Wait... 1 291

V Tag Data V Tag Data 0 0 000 00 00 00 00 0 000 00 00 00 00 1 1 291 0F 1E 39 EC 0 000 00 00 00 00 2 0 000 00 00 00 00 0 000 00 00 00 00 3 0 000 00 00 00 00 0 000 00 00 00 00 1 547 Access address 0x2234 = 0010 0010 0011 0100 Offset = 0 Index = 1 Tag = 547 Miss. Request from next level. Wait...

V Tag Data V Tag Data 0 0 000 00 00 00 00 0 000 00 00 00 00 1 1 291 0F 1E 39 EC 1 547 01 CF D0 87 2 0 000 00 00 00 00 0 000 00 00 00 00 3 0 000 00 00 00 00 0 000 00 00 00 00 Access address 0x1234 = 0001 0010 0011 0100 Offset = 0 Index = 1 Tag = 291 Hit in Way 0

56 Cache Miss Paper Simulation • 8B cache, 2B blocks,
2 ways Set 0 Set 1 Address Tag Index Offset Way0 Way1 Way0 Way1 Result C invalid 0 0 1 E 8 3 8 0 8 4 6 • What happens for each request?

57 Cache Miss Paper Simulation • 8B cache, 2B blocks,
2 ways à 2 sets (=8/2/2) Set 0 Set 1 Address Tag Index Offset Way0 Way1 Way0 Way1 Result C 3 0 0 invalid 0 0 1 Miss E 3 1 0 3 0 0 1 Miss 8 2 0 0 3 0 0 3 Miss 3 0 1 1 3 2 0 3 Hit 8 2 0 0 3 2 0 3 Hit 0 0 0 0 3 2 0 3 Miss 8 2 0 0 0 2 0 3 Hit 4 1 0 0 0 2 0 3 Miss 6 1 1 0 0 1 0 3 Miss • Offset: 1 bit. Index: 1 bit

Cache miss paper

Cache miss paper

Chen

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36 Cache Miss Paper Simulation • 8B cache, 2B blocks

40 Cache Miss Paper Simulation • 8B cache, 2B blocks

46 Cache Miss Paper Simulation (4B instead 2B blocks) •

47 Cache Miss Paper Simulation (4B instead 2B blocks) •

52 Cache Behavior in 2-ways Set # Way 0 Way

53 Cache Behavior 2-ways Set # Way 0 Way 1

54 Cache Behavior 2-ways Set # Way 0 Way 1

55 Cache Behavior 2-ways Set # Way 0 Way 1

56 Cache Miss Paper Simulation • 8B cache, 2B blocks,

57 Cache Miss Paper Simulation • 8B cache, 2B blocks,