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Multi cycle DataPath

Tiffany
October 05, 2022

Multi cycle DataPath

Tiffany

October 05, 2022
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  1. 36
    One Alternative to Single-Cycle DP: Multi-Cycle DP
    • Cuts datapath into multiple stages (5 here), isolated using registers
    • FSM control “walks” insns thru stages (by staging control signals)
    + Insns can bypass stages and exit early
    P
    C
    Insn
    Mem
    Register
    File
    S
    X
    s1 s2 d
    Data
    Mem
    a
    d
    +
    4
    <<
    2
    I
    R D
    O
    B
    A
    s3
    s3
    s3 s4
    s5
    s5
    s5

    View Slide

  2. 46
    Multi-Cycle Datapath Example: Add
    P
    C
    Insn
    Mem
    Register
    File
    S
    X
    s1 s2 d
    Data
    Mem
    a
    d
    +
    4
    <<
    2
    I
    R D
    O
    B
    A
    • Example: Add
    • Cycle 1: Read IMEM

    View Slide

  3. 47
    Multi-Cycle Datapath Example: Add
    P
    C
    Insn
    Mem
    Register
    File
    S
    X
    s1 s2 d
    Data
    Mem
    a
    d
    +
    4
    <<
    2
    I
    R D
    O
    B
    A
    • Example: Add
    • Cycle 1: Read IMEM
    • Cycle 2: Decode + Read RF

    View Slide

  4. 48
    Multi-Cycle Datapath Example: Add
    P
    C
    Insn
    Mem
    Register
    File
    S
    X
    s1 s2 d
    Data
    Mem
    a
    d
    +
    4
    <<
    2
    I
    R D
    O
    B
    A
    • Example: Add
    • Cycle 1: Read IMEM
    • Cycle 2: Decode + Read RF
    • Cycle 3: ALU

    View Slide

  5. 49
    Multi-Cycle Datapath Example: Add
    P
    C
    Insn
    Mem
    Register
    File
    S
    X
    s1 s2 d
    Data
    Mem
    a
    d
    +
    4
    <<
    2
    I
    R D
    O
    B
    A
    • Example: Add
    • Cycle 1: Read IMEM
    • Cycle 2: Decode + Read RF
    • Cycle 3: ALU
    • Cycle 4: Writeback + Increment PC

    View Slide

  6. 50
    Multi-Cycle Datapath Performance
    • Opposite performance split of single-cycle datapath
    + Short clock period
    – High CPI
    P
    C
    Insn
    Mem
    Register
    File
    S
    X
    s1 s2 d
    Data
    Mem
    a
    d
    +
    4
    <<
    2
    I
    R D
    O
    B
    A

    View Slide