Towards a True Programmable Blockchain World: An Introduction to CKB VM

Transcript

1. Towards a True Programmable
   Blockchain World:
   An Introduction to CKB VM
   Xuejie Xiao (x@nervos.org)
   

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2. Design a Blockchain VM
   Build a performant VM with Rust
   Q&A
   Agenda
   

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3. Design a Blockchain VM
   Build a performant VM with Rust
   

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4. ● Determinism.
   ● Security.
   

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5. ● Flexible enough to support any use case, yet simple
   enough to reduce attack surface.
   ○ Backwards compatibility.
   ● Industrial support.
   ○ Innovation is good, but no need to reinvent
   everything
   ● Reasonable & future-proof runtime cost model.
   ○ Estimable resource usage
   

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6. CKB VM builds on RISC-V
   RISC-V is an & ISA (instruction set architecture) enabling a new era of
   innovation for processor architectures.
   CKB VM is a software implementation of RISC-V following its current standards.
   

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7. CKB VM works more like a real CPU
   int fib(int n) {
   int a = 0, b = 1, c, i;
   if (n == 0) return a;
   for (i = 2; i <= n; i++) {
   c = a + b;
   a = b;
   b = c;
   }
   return b;
   }
   fib:
   li a5,0
   beqz a0,.L2
   li a4,2
   li a5,1
   li a3,0
   .L3:
   ble a4,a0,.L4
   .L2:
   mv a0,a5
   ret
   .L4:
   addw a2,a3,a5
   addiw a4,a4,1
   mv a3,a5
   mv a5,a2
   j .L3
   

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8. RISC-V is supported by the industry
   Source: https://content.riscv.org/wp-content/uploads/2017/12/Tue0900-StateOfUnion-krste.pdf
   

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9. RISC-V is supported by the industry
   Source: https://archive.fosdem.org/2018/schedule/event/riscv/
   

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10. RISC-V is supported by the industry
    Source: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133724.html
    

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11. RISC-V is supported by the industry
    Source: https://people.debian.org/~mafm/posts/2019/20190617_debian-gnulinux-riscv64-port-in-mid-2019/
    

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12. RISC-V is supported by the industry
    Source: https://github.com/golang/go/issues/27532
    

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13. RISC-V is supported by the industry
    Source: https://github.com/rust-lang/rust/pulls?utf8=%E2%9C%93&q=is%3Apr+RISC-V+is%3Amerged+
    

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15. RISC-V is minimal
    Source: https://www.cl.cam.ac.uk/teaching/1617/ECAD+Arch/files/docs/RISCVGreenCardv8-20151013.pdf
    

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16. RISC-V is minimal
    Source: https://www.cl.cam.ac.uk/teaching/1617/ECAD+Arch/files/docs/RISCVGreenCardv8-20151013.pdf
    

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17. RISC-V is minimal
    Source: https://www.cl.cam.ac.uk/teaching/1617/ECAD+Arch/files/docs/RISCVGreenCardv8-20151013.pdf
    Only 103 instructions!
    

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18. RISC-V is flexible
    ● Essentially a computer embedded in a blockchain
    ● More than adequate for existing use cases(ERC20 tokens, atomic
    swaps, etc.)
    ● Enables new use cases
    

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19. CKB VM enables new use cases
    ● The world has numerous crypto algorithms, which
    one should we use?
    ● Compile secp256k1 via GCC to RISC-V, then deploy
    it on CKB.
    ● No need to wait for precompiles. Deploy your
    favorite algorithm as you wish.
    ● Your contracts are treated exactly the as the
    official ones.
    

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21. CKB VM enables new use cases
    ● Solidity is fading, what should I do with my current
    dapp?
    ● Compile an existing blockchain VM(Bitcoin Script,
    EVM, …) to RISC-V, then deploy it on CKB.
    ● Preserve , keep a more ,
    ecosystem.
    

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22. CKB VM enables new use cases
    ● What if I want to use JavaScript and enjoy the
    rich npm ecosystem?
    ● Compile a JS implementation(e.g: duktape) to
    RISC-V, then deploy to CKB.
    ● Performance might or might not be a problem, it
    greatly depends on the use case.
    ○ As adoption grows, optimizations will be
    applied due to economy.
    

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23. CKB VM enables new use cases
    

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24. CKB VM enables new use cases
    WebAssembly makes a lot of sense for Web, but remains
    for blockchains.
    

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25. Is WebAssembly the right choice?
    Existing quirks: heap
    ● Low level languages(C/C++, Rust, Go, etc.) typically
    require heaps for dynamic allocations.
    ● WebAssembly only allows declaring fixed length
    buffer in modules in advance.
    ● To implement a growable heap, typical solution is
    to create an ArrayBuffer in JavaScript, then expose
    it to WebAssembly.
    ● This works for Web, but what about blockchains?
    

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26. Is WebAssembly the right choice?
    Existing quirks: non-determinism
    Source: https://webassembly.org/docs/rationale/
    “Nondeterminism is only specified as a compromise when there is no
    other practical way to:
    - Achieve portable native performance.
    - Lower resource usage.
    - Reduce implementation complexity (both of WebAssembly VMs
    as well as compilers generating WebAssembly binaries).
    - Allow usage of new hardware features.
    - Allows implementations to security-harden certain usecases.”
    

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27. Is WebAssembly the right choice?
    Existing quirks: non-determinism
    Source: https://webassembly.org/docs/rationale/
    “As WebAssembly gets implemented and tested with multiple
    languages on multiple architectures we may revisit some of the
    design decisions:
    - (omitted …)
    - When different languages have different expectations then it’s
    unfortunate if WebAssembly measurably penalizes one’s
    performance by enforcing determinism which that language
    doesn’t care about, but which another language may want.”
    

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28. Is WebAssembly the right choice?
    Ton of planned features
    Source: https://webassembly.org/docs/future-features/
    

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29. Is WebAssembly the right choice?
    Ton of planned features
    Source: https://webassembly.org/docs/future-features/
    

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30. Is WebAssembly the right choice?
    Ton of planned features
    Source: https://webassembly.org/docs/future-features/
    

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31. Is WebAssembly the right choice?
    Ton of planned features
    Source: https://webassembly.org/docs/future-features/
    

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32. CKB VM enables new use cases
    

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33. CKB VM enables new use cases
    ● WASM => RISC-V transpiler.
    ● Ship higher-level features(GC, Tail Call, Expressive
    Control Flows, Floating Point calculations, etc.) in
    your contract as used.
    ● Evergreen WASM implementation.
    

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35. RISC-V has a decent cost model
    ● As an ISA for a real CPU, each RISC-V instruction has a cost
    called .
    ● As a real computer model, CKB VM can work in a ,
    memory space.
    

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36. Hardware based CKB VM
    ● A lucky accident
    ● Real RISC-V CPU can be attached to accelerate CKB VM
    executions further.
    ● Suitable for cases where higher TPS is required, e.g., exchanges,
    mining pools.
    

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38. Design a Blockchain VM
    Build a performant VM with Rust
    

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39. Numbers
    Runner type Runtime Ratio
    Native 0.124 ms 1x
    CKB VM (Interpreter) 6.9ms 55.6x
    CKB VM (AOT JIT) 1ms 8x
    Wasmer (Cranelift) 1ms 8x
    Wasmer (LLVM) 0.84ms 6.7x
    

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40. Numbers
    Runner type Runtime Ratio LOC
    Native 0.124 ms 1x
    CKB VM (Interpreter) 6.9ms 55.6x 8484
    CKB VM (AOT JIT) 1ms 8x 8484
    Wasmer (Cranelift) 1ms 8x 36830(wasmer) +
    62266(cranelift) = 99096
    Wasmer (LLVM) 0.84ms 6.7x ?
    Counted via: cloc --not-match-f='generated|compiled|test|example' --fullpath .
    

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41. Numbers
    Runner type Runtime Ratio LOC
    Native 0.124 ms 1x
    CKB VM (Interpreter) 6.9ms 55.6x 8484
    CKB VM (AOT JIT) 1ms 8x 8484
    Wasmer (Cranelift) 1ms 8x 36830(wasmer) +
    62266(cranelift) = 99096
    Wasmer (LLVM) 0.84ms 6.7x ?
    Those are not designed for blockchains!
    Counted via: cloc --not-match-f='generated|compiled|test|example' --fullpath .
    

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42. ● : RISC-V is much closer to
    real hardware
    ● Rust balances between code clarity and low level
    control
    ● Leverage RAW assembly for hot loops.
    ● Rust is awesome in most cases, but watch out for
    quirks
    

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43. pub enum Instruction {
    I(i::Instruction),
    // omitted
    }
    pub enum i::Instruction {
    R(Rtype),
    // omitted
    }
    pub struct Rtype {
    rs1: usize,
    rd: usize,
    imm: usize,
    inst: i32,
    }
    32 bytes
    40 bytes
    48 bytes
    

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44. 63 0
    +-----+-----+-----+-----+-----+-----+-----+-----+
    | | rs1 | rs2 | res | | rd | op | R-type
    +-----------+-----------------------------------+
    | immediate | rs1 | res | | rd | op | I-type
    +-----------------------------------------------+
    | immediate | rs1 | res | | rs2 | op | S-type/B-type
    +-----------------+-----------------------------+
    | immediate | res | | rd | op | U-type/J-type
    +-----+-----+-----+-----+-----+-----+-----+-----+
    

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45. pub enum Foo {
    Bar(u64),
    Baz(u8),
    Hah(u32),
    Lol(u16),
    }
    fn pp(f: &Foo) {
    match f {
    Foo::Bar(i) => println!("Bar {}", i),
    Foo::Baz(j) => println!("Baz {}", j),
    Foo::Hah(h) => println!("Hah {}", h),
    Foo::Lol(l) => println!("Lol {}", l),
    };
    }
    

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46. playground::pp:
    subq $72, %rsp
    movzbl (%rdi), %eax
    cmpq $1, %rax
    je .LBB9_4
    cmpq $2, %rax
    je .LBB9_5
    cmpq $3, %rax
    jne .LBB9_3
    

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47. Source: https://github.com/xxuejie/ckb-vm/commit/78edc2ed195df78c69795830e89c97c67e43b569
    

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48. Source: http://lua-users.org/lists/lua-l/2011-02/msg00742.html
    

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49. Source: https://www.reddit.com/r/programming/comments/badl2/luajit_2_beta_3_is_out_support_both_x32_x64/c0lrus0/
    // Prologue for type ABC instructions (others have a zero prologue).
    movzx ebp, ah Decode RC (split of RD)
    movzx eax, al Decode RB (split of RD)
    // The instruction itself.
    cmp [edx+ebp*8+0x4], -13 Type check of [RB]
    ja ->lj_vmeta_arith_vn
    movsd xmm0, [edx+ebp*8] Load of [RB]
    addsd xmm0, [edi+eax*8] Add to [RC]
    movsd [edx+ecx*8], xmm0 Store in [RA]
    // Standard epilogue: decode + dispatch the next instruction.
    mov eax, [esi] Load next bytecode
    movzx ecx, ah Decode RA
    movzx ebp, al Decode opcode
    add esi, 0x4 Increment PC
    shr eax, 0x10 Decode RD
    jmp [ebx+ebp*4] Dispatch to next instruction
    Inspirations from masters
    

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50. 13 instructions for 1 RISC-V instruction
    movzx edx,cl
    movzx ebp,ch
    mov rdx,QWORD PTR [rsi+rdx*8]
    add rdx,QWORD PTR [rsi+rbp*8]
    mov QWORD PTR [rsi+rax*8],rdx
    mov QWORD PTR [rsi],0x0
    mov rcx,QWORD PTR [r9]
    add r9,0x8
    movzx eax,ch
    sar rcx,0x20
    mov rdi,QWORD PTR [r8]
    add r8,0x8
    jmp rdi
    Decode operands
    Actual work
    Decode next instruction
    

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51. 13 instructions for 1 RISC-V instruction
    movzx edx,cl
    movzx ebp,ch
    mov rdx,QWORD PTR [rsi+rdx*8]
    add rdx,QWORD PTR [rsi+rbp*8]
    mov QWORD PTR [rsi+rax*8],rdx
    mov QWORD PTR [rsi],0x0
    mov rcx,QWORD PTR [r9]
    add r9,0x8
    movzx eax,ch
    sar rcx,0x20
    mov rdi,QWORD PTR [r8]
    add r8,0x8
    jmp rdi
    Decode operands
    Actual work
    Decode next instruction
    This is our interpreter
    

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52. Can we save more?
    movzx edx,cl
    movzx ebp,ch
    mov rdx,QWORD PTR [rsi+rdx*8]
    add rdx,QWORD PTR [rsi+rbp*8]
    mov QWORD PTR [rsi+rax*8],rdx
    mov QWORD PTR [rsi],0x0
    mov rcx,QWORD PTR [r9]
    add r9,0x8
    movzx eax,ch
    sar rcx,0x20
    mov rdi,QWORD PTR [r8]
    add r8,0x8
    jmp rdi
    Overhead
    Actual work
    Overhead
    

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53. ● Translate RISC-V assembly directly to X86-64
    assembly
    ● In most cases, VM can run in X86-64 generated
    code directly
    ● Fallback to assembly interpreter in rare cases
    ● Rust’s zero cost JIT helps a lot!
    

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54. ● Rust in most places for safety and clarity
    ● Assembly in few places for absolute speed
    -------------------------------------------------------------------------------
    Language files blank comment code
    -------------------------------------------------------------------------------
    Rust 31 611 341 5567
    C 1 131 75 1087
    Assembly 1 23 94 982
    

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56. Thank You!
    Questions?
    www.nervos.org
    github.com/nervosnetwork
    

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