Survey of Transactional Memory

Transactional Memory Yuuki Takano (NICT) [email protected]

8IZ5SBOTBDUJPOBM .FNPSZ w MPDLJTEJ⒏DVMUUPNBOBHF w EFBEMPDL w TUBSWBUJPO w QSJPSJUZ*OWFSTJPO
w MPDLDPOWPZ w USBOTBDUJPOBMNFNPSZNJUJHBUFTUIFTFQSPCMFNT 2

%FBEMPDL 3 t Thread 1 Thread 2 Lock B Lock
A try to acquire A and fail try to acquire B and fail

4UBSWBUJPO 4 t High Priority Thread (acquire A) High Priority
Thread (acquire B) Lock B Lock A Low Priority Thread (acquire A and B) try to acquire A and fail Lock A try to acuire B and fail Lock A Release A

1SJPSJUZ*OWFSTJPO 5 t High Priority Thread Low Priority Thread acquiring
lock try to acquire and fail

-PDL$POWPZ 6 Scheduler Thread1 Thread2 Thread3 ThreadN 1. contention Thread2
4. acquire 2. event 3. contention (spin lock) 4. reschedule high overhead when many threads

$PNQMFYJUZPG .VMUJUISFBE1SPHSBNNJOH 7 algorithm data structure ideal world algorithm data
structure parallelism parallel algorithm parallel data structure real world complicated source code simple source code buggy difﬁcult to maintain actually we want

-PDLBOE 5SBOTBDUJPOBM.FNPSZ w -PDL w FYFDVUFDSJUJDBMTFDUJPOFYDMVTJWFMZ w POMZPOFDPEFFOUFSUIFDSJUJDBMTFDUJPO w 5SBOTBDUJPOBM.FNPSZ
w FYFDVUFDSJUJDBMTFDUJPOTQFDVMBUJWFMZ w NVMUJQMFDPEFTFOUFSTBNFDSJUJDBMTFDUJPOTJNVMUBOFPVTMZ w DPOqJDUTBSFEFUFDUFECPUIXIJMFFYFDVUJOHDSJUJDBMTFDUJPOBOEUIFFOE PGDSJUJDBMTFDUJPO 8

4QJOMPDLCZ"UPNJD0QFSBUJPO w $"4 DPNQBSFBOETXBQ w DPNQBSFBOETXBQBSFQFSGPSNFEBUPNJDBMMZ w UFTUBOETFU DPNQBSFBOEBEE
FUDʜ w TQJOMPDLJTBDIJFWFECZVTJOH$"4 9 int locked; lock_spin() { while (__sync_lock_test_and_set(&locked, 1)) { while (locked) ; // busy-wait } } unlock_spin() { __sync_lock_release(&locked); } JGMPDLFEJT TFU

4ZOUBYPG5SBOTBDUJPOBM.FNPSZ BUPNJD SFUSZ PS&MTF 10 atomic { // transaction if
(q.size() == 0) { // rollback and retry // transactions is restarted when // read-set is updated retry; } … // do something } orElse { // detect rollback and retry }

4PGUXBSF 5SBOTBDUJPOBM.FNPSZ 11

4PGUXBSF5SBOTBDUJPOBM .FNPSZ w 5- w %BWF%JDF 0SJ4IBMFW BOE/JS4IBWJUl5SBOTBDUJPOBMMPDLJOH**z UI*OUFSOBUJPOBM$POGFSFODFPO %JTUSJCVUFE$PNQVUJOHz
%*4$ w -4" w 5PSWBME3JFHFM 1BTDBM'FMCFS BOE$ISJTUPG'FU[FS l"-B[Z4OBQTIPU"MHPSJUINXJUI&BHFS 7BMJEBUJPOz UI*OUFSOBUJPOBM$POGFSFODFPO%JTUSJCVUFE$PNQVUJOH %*4$ w -PH5. w ,FWJO&.PPSF +BZBSBN#PCCB .JDIFMMF+.PSBWBO .BSL%)JMM %BWJE"8PPE l-PH5.MPH CBTFEUSBOTBDUJPOBMNFNPSZz )1$" w %&6$& w (VZ,PSMBOE /JS4IBWJUBOE1BTDBM'FMCFS l/POJOWBTJWF+BWB$PODVSSFODZXJUI%FVDF45.z .VMUJ1SPH 12 FUD

4VNNBSZPG5- w QSFQBSFBWBSJBCMFDBMMFEHMPCBMDMPDL w BTTPDJBUFNFNPSZSFHJPOTXJUIWFSTJPOOVNCFST w VQEBUFWFSTJPOOVNCFSTXIFOXSJUJOH w EFUFDUDPOqJDUTXIFOSFBEJOHBOEXSJUJOHCZDPNQBSJOHUIF HMPCBMDMPDLXJUINFNPSZWFSTJPOOVNCFS
w SFUSZUSBOTBDUJPOXIFOEFUFDUJOHDPOqJDUT w PUIFSXJTFDPNNJU 13

5-7BSJBCMFT 14 HMPCBMWFSTJPODMPDL WBSJBCMF WFSTJPOOVNCFS (MPCBM.FNPSZ 5ISFBE-PDBM.FNPSZ SFBEWFSTJPOOVNCFS XSJUFMPDL WBSJBCMF
WFSTJPOOVNCFS XSJUFMPDL WBSJBCMF WFSTJPOOVNCFS XSJUFMPDL XSJUFWFSTJPOOVNCFS UISFBE SFBETFU XSJUFTFU

5-"MHPSJUIN 15 HMPCBMWFSTJPODMPDL WBSJBCMF WFSTJPOOVNCFS (MPCBM.FNPSZ 5ISFBE-PDBM.FNPSZ SFBEWFSTJPOOVNCFS XSJUFMPDL
WBSJBCMF WFSTJPOOVNCFS XSJUFMPDL WBSJBCMF WFSTJPOOVNCFS XSJUFMPDL XSJUFWFSTJPOOVNCFS UISFBE SFBETFU XSJUFTFU transaction { load var1; load var2; … store var3; } MPBEUIFHMPCBMWFSTJPODMPDLBOETUPSFJUJOB UISFBEMPDBMSFBEWFSTJPOOVNCFS

WBSJBCMF WFSTJPOOVNCFS XSJUFMPDL WBSJBCMF WFSTJPOOVNCFS XSJUFMPDL XSJUFWFSTJPOOVNCFS UISFBE SFBETFU XSJUFTFU SVOUISPVHIBTQFDVMBUJWFFYFDVUJPO transaction { load var1; load var2; … store var3; } SVO

WBSJBCMF WFSTJPOOVNCFS XSJUFMPDL WBSJBCMF WFSTJPOOVNCFS XSJUFMPDL XSJUFWFSTJPOOVNCFS UISFBE SFBETFU XSJUFTFU MPHSFBEBEESFTTFTUPUIFSFBETFU transaction { load var1; load var2; … store var3; } MPHSFBETFU

WBSJBCMF WFSTJPOOVNCFS XSJUFMPDL WBSJBCMF WFSTJPOOVNCFS XSJUFMPDL XSJUFWFSTJPOOVNCFS UISFBE SFBETFU XSJUFTFU MPHXSJUFBEESFTTFTBOEWBMVFTUP UIFXSJUFTFU transaction { load var1; load var2; … store var3; } MPHXSJUFTFU

5-"MHPSJUIN 19 HMPCBMWFSTJPODMPDL WBSJBCMF WFSTJPOOVNCFS (MPCBM.FNPSZ 5ISFBE-PDBM.FNPSZ XSJUFMPDL WBSJBCMF
WFSTJPOOVNCFS XSJUFMPDL WBSJBCMF WFSTJPOOVNCFS XSJUFMPDL UISFBE QPJOUFSUP QPJOUFSUP SFBETFU QPJOUFSUP XSJUFTFU QPJOUFSUP WBMVFPG WBSJBCMFJTTUPSFEBOEMPBEFE /PUFUIBUJGBWBSJBCMFJOUIFSFBETFUBMSFBEZBQQFBST JOUIFXSJUFTFU SFGFSUPUIFWBSJBCMFJOUIFXSJUFTFU GSPNUPBWPJESFBEBGUFSXSJUFIB[BSE

WBSJBCMF WFSTJPOOVNCFS XSJUFMPDL WBSJBCMF WFSTJPOOVNCFS XSJUFMPDL XSJUFWFSTJPOOVNCFS UISFBE SFBETFU XSJUFTFU DIFDLWBSJBCMFTBSFOPUNPEJpFEXIFO MPBEJOHNBLFTVSFUIBUWFSTJPOOVNCFSTBSF MFTTUIBOUIFSFBEWFSTJPOOVNCFS transaction { load var1; load var2; … store var3; } JGNPEJpFE BCPSUUSBOTBDUJPO

WBSJBCMF WFSTJPOOVNCFS XSJUFMPDL WBSJBCMF WFSTJPOOVNCFS XSJUFMPDL XSJUFWFSTJPOOVNCFS UISFBE SFBETFU XSJUFTFU DIFDLXSJUFMPDLTBSFGSFF transaction { load var1; load var2; … store var3; } GSFF GSFF JGMPDLFE BCPSUUSBOTBDUJPO

WBSJBCMF WFSTJPOOVNCFS XSJUFMPDL WBSJBCMF WFSTJPOOVNCFS XSJUFMPDL XSJUFWFSTJPOOVNCFS UISFBE SFBETFU XSJUFTFU BDRVJSFXSJUFMPDLTVTJOHCPVOEFETQJOMPDL transaction { load var1; load var2; … store var3; } MPDL JGGBJMFEUPBDRVJSFXSJUFMPDLMPDLFE BCPSUUSBOTBDUJPO

WBSJBCMF WFSTJPOOVNCFS XSJUFMPDL WBSJBCMF WFSTJPOOVNCFS XSJUFMPDL XSJUFWFSTJPOOVNCFS UISFBE SFBETFU XSJUFTFU JODSFNFOUUIFHMPCBMWFSTJPODMPDL $"4PQFSBUJPO BOETUPSFJUUPUIFXSJUFWFSTJPOOVNCFS transaction { load var1; load var2; … store var3; } JODSFNFOU BOETUPSF

WBSJBCMF WFSTJPOOVNCFS XSJUFMPDL WBSJBCMF WFSTJPOOVNCFS XSJUFMPDL XSJUFWFSTJPOOVNCFS UISFBE SFBETFU XSJUFTFU DIFDLWBSJBCMFTBSFOPUNPEJpFEXIFO MPBEJOHNBLFTVSFUIBUWFSTJPOOVNCFSTBSF MFTTUIBOUIFSFBEWFSTJPOOVNCFS transaction { load var1; load var2; … store var3; } JGNPEJpFE BCPSUUSBOTBDUJPO

WBSJBCMF WFSTJPOOVNCFS XSJUFMPDL WBSJBCMF WFSTJPOOVNCFS XSJUFMPDL XSJUFWFSTJPOOVNCFS UISFBE SFBETFU XSJUFTFU DIFDLXSJUFMPDLTBSFGSFF transaction { load var1; load var2; … store var3; } GSFF GSFF JGMPDLFE BCPSUUSBOTBDUJPO

WBSJBCMF WFSTJPOOVNCFS XSJUFMPDL WBSJBCMF WFSTJPOOVNCFS XSJUFMPDL XSJUFWFSTJPOOVNCFS UISFBE SFBETFU XSJUFTFU transaction { load var1; load var2; … store var3; } SW XW JOUIFTQFDJBMDBTF XIFSFSFBEWFSTJPO OVNCFS XSJUFWFSTJPOOVNCFS JUJTOPU OFDFTTBSZUPWBMJEBUFUIFSFBETFU 

WBSJBCMF WFSTJPOOVNCFS XSJUFMPDL WBSJBCMF WFSTJPOOVNCFS XSJUFMPDL XSJUFWFSTJPOOVNCFS UISFBE SFBETFU XSJUFTFU transaction { load var1; load var2; … store var3; } DPNNJUWBMVFTPGUIFXSJUFTFU 

WBSJBCMF WFSTJPOOVNCFS XSJUFMPDL WBSJBCMF WFSTJPOOVNCFS XSJUFMPDL XSJUFWFSTJPOOVNCFS UISFBE SFBETFU XSJUFTFU transaction { load var1; load var2; … store var3; } VQEBUFWFSTJPOOVNCFSTCZUIF XSJUFWFSTJPOOVNCFS SFMFBTF

WBSJBCMF WFSTJPOOVNCFS XSJUFMPDL WBSJBCMF WFSTJPOOVNCFS XSJUFMPDL XSJUFWFSTJPOOVNCFS UISFBE SFBETFU XSJUFTFU transaction { load var1; load var2; … store var3; } SFMFBTFUIFXSJUFMPDLT SFMFBTF

)BSEXBSF 5SBOTBDUJPOBM.FNPSZ 30

)BSEXBSF5SBOTBDUJPOBM .FNPSZ w VTF$16DBDIFUPEFUFDUDPOqJDUT w NPEJGZDBDIFDPIFSFODFBMHPSJUINUP BDIJFWFUSBOTBDUJPOBMNFNPSZ 31

$BDIF$PIFSFODF w .&4*QSPUPDPM w 5IFSFBSFTUBUFT w .PEJpFE &YDMVTJWF 4IBSFE *OWBMJE
32

.&4* .PEJpFE4UBUF 33 main memory CPU0 CPU1 cache 0 cache
1 cache line dirty, must write back not shared with other CPU

.&4* &YDMVTJWF4UBUF 34 main memory CPU0 CPU1 cache 0 cache
1 cache line not modiﬁed not shared with other CPU

.&4* 4IBSFE4UBUF 35 main memory CPU0 CPU1 cache 0 cache
1 cache line not modiﬁed shared with other CPU

.&4* *OWBMJE4UBUF 36 main memory CPU0 CPU1 cache 0 cache
1 cache line no meaningful data

.&4* &YDMVTJWF-PBE 37 main memory CPU0 CPU1 cache 0 cache
1 1. request exclusive load 2. write back if modiﬁed 3. change state to invalid 4. load state with exclusive state

.&4* 4IBSFE-PBE 38 main memory CPU0 CPU1 cache 0 cache
1 1. request shared load 2. write back if modiﬁed 3. change state to shared 4. load state with shared state

.&4* FWJDUJPO 39 main memory CPU0 CPU1 cache 0 cache
1 1. write back if modiﬁed 2. discard

5SBOTBDUJPOBM $BDIF$PIFSFODF 40 main memory CPU0 CPU1 cache 0
cache 1 0 prepare transactional bit in each cache line 0: not in transaction 1: in transaction

cache 1 1 abort transaction if MESI protocol invalidates transaction entry shared or exclusive state

cache 1 1 discard modiﬁed value and abort transaction if MESI protocol invalidates or evicts transaction entry modiﬁed

cache 1 1 abort transaction if MESI protocol evicts transaction entry because cache coherence protocol cannot detect conﬂicts evicted

1SPCMFNT 44

1SPCMFN w JOpOJUFMPPQJOUSBOTBDUJPO w EFUFDUJPOPGWBSJBCMFWFSTJPOJOMPPQTTIPVMESFEVDF QFSGPSNBODFTJHOJpDBOUMZ w SFRVJSFNFOUPGDMPTFENFNPSZNBOBHFNFOU w
DPEFTPVUPGUSBOTBDUJPODBOSFGFSBOEVQEBUFWBSJBCMFT JOUSBOTBDUJPOJOMBOHVBHFTMJLF$ $ w DPNQJMFSPSSVOOJOHFOWJSPONFOUTIPVMEDBSFBCPVU 45

1SPCMFN 46 atomic { … launchMissile(); … } .JTTJMFTNBZCF
MBVODIFENBOZUJNFT *0JOUSBOTBDUJPONVTUDBVTFTBCPSU

1SPCMFN w MJWFMPDL 47

*NQMFNFOUBUJPO 48

4PGUXBSF5SBOTBDUJPOBM.FNPSZ 45. JO)BTLFMM w )BTLFMMQSPWJEFT45.CZDPODVSSFOUNPEVMF w 45.NPOBEJTQSPWJEFEUPBDIJFWF45. w FYBNQMFJNQMFNFOUBUJPO
w IUUQTHJTUHJUIVCDPNZUBLBOP CFGDCEEGD 49

)BSEXBSF5SBOTBDUJPOBM.FNPSZ )5. *OUFM549 w )5.JTBWBJMBCMFGSPN)BTXFMM w *OUFM549)-& w YBDRVJSFBOEYSFMFBTFJOTUSVDUJPOT
w *OUFM54935. w YCFHJOBOEYFOEJOTUSVDUJPOT 50

*OUFM54935. 51 xbegin ABORT . . . xend ABORT: //
fallback if aborted sometimes, must go to fallback codes (such as spin lock)

-PDLCZVTJOHUTYUPPMT IUUQTHJUIVCDPNBOEJLMFFOUTYUPPMT 52 volatile int lock = 0; rtm_lock() {
for (int i = 0; i < RTM_MAX_RETRY; i++) { unsigned status = _xbegin(); if (status == _XBEGIN_STARTED) { if (! lock) return; // successfully started _xabort(0xff); } if ((status & _XABORT_EXPLICIT) && _XABORT_CODE(status) == 0xff && ! (status & _XABORT_NESTED) { while (lock) _mm_pause(); // busy-wait } else if (!(status & _XABORT_RETRY)) { break; } } while (__sync_lock_test_and_set(&lock, 1)) { // fallback to spin-lock while (lock) _mm_pause(); // busy-wait } } MPDLCZVTJOH*OUFM54935.

6OMPDLCZVTJOHUTYUPPMT IUUQTHJUIVCDPNBOEJLMFFOUTYUPPMT 53 rtm_unlock() { if (lock) { __sync_lock_release(&lock); }
else { _xend(); } } VOMPDLCZVTJOH*OUFM54935.

1FSGPSNBODFPG*OUFM549 w *OUFMTBZTUIBUDPEFTPGDPBSTFHSBJOFE MPDLDBODPNQBSFXJUIDPEFTPGpOF HSBJOFEMPDL w FBTZUPXSJUFDPSFTDBMBCMFDPEFT 54

55 Applying Intel® TSX scaling Threads scaling Threads Application with
Coarse Grain Lock Application re-written with Finer Grain Locks An example of secondary benefits of Intel® TSX Coarse Grain Lock Coarse Grain Lock + Intel® TSX Fine Grain Locks Fine Grain Locks + Intel® TSX Fine Grain Behavior at Coarse Grain Effort GSPN*OUFM%FWFMPQFS'PSVN

56 Intel® TSX Can Enable Simpler Scalable Algorithms Enabling Simpler
Algorithms Lock-Free Algorithm • Don’t use critical section locks • Developer manages concurrency • Very difficult to get correct & optimize – Constrain data structure selection – Highly contended atomic operations State of the art lock-free algorithm Ops/sec Threads Ops/sec Threads TSX lock based algorithm Lock-Based + Intel® TSX • Use critical section locks for ease • Let hardware extract concurrency • Enables algorithm simplification – Flexible data structure selection – Equivalent data structure lock-free algorithm very hard to verify Real World Example GSPN*OUFM%FWFMPQFS'PSVN

&0' 57

Survey of Transactional Memory

Survey of Transactional Memory

More Decks by ytakano

Other Decks in Research

Featured

Transcript