ALOE Webinar

ALOE is a framework for real-time distributed SDR processing

Transcript

1. ALOE Webinar. May 24th 2012. http://flexnets.upc.edu/ Department of Signal Theory and Communications UNIVERSITAT POLITÈCNICA DE CATALUNYA ALOE Framework and Tools Vuk Marojevic Ismael Gomez Antoni Gelonch
2. ALOE Webinar. May 24th 2012. http://flexnets.upc.edu/ LTE ? Core3 DSP DSP Core1 μProc Core4 Core2 SDR Execution Environment SDR Application 2 (Waveform 2) Core3 DSP DSP Core1 Core4 Core2 DSP SDR Application N (Waveform N) core3 DSP DSP core1 ARM core4 core2 ARM SDR Execution Environment
3. ALOE Webinar. May 24th 2012. http://flexnets.upc.edu/ Pipelined Execution + Online Mapping Flexible Multiprocessing Flexible Low Overhead ALOE Simplified Scheduling
4. ALOE Webinar. May 24th 2012. http://flexnets.upc.edu/ Outline 1. ALOE Framework 2. Computing Resource Management 3. ALOE Tools 4. Waveform Development 5. Summary
5. ALOE Webinar. May 24th 2012. http://flexnets.upc.edu/ ▫ How to design a low-overhead framework? Language Memory Scheduling Standard C Static (or custom pool) Static, non-preemptive 1.1 Lightweight Framework
6. 2 3 … m ALOE VIRTUAL PLATFORM PE1 PE2 PE2 Abstract Application Layer Real Application Layer ALOE Layer Hardware Layer ALOE 1 1.2 ALOE Layers ALOE ALOE PE: Processing Element
7. ALOE Webinar. May 24th 2012. http://flexnets.upc.edu/ HARDWARE Operating System (optional) API ALOE Hardware Library (service to upper ALOE layers) API ALOE Software Lib (service to modules) API FRONT END SW LOAD SYNC STATS EXEC CTRL BRIDGE CMD MAN SW MAN STATS MAN SYNC MAST SW MAP ALOE Software Daemons MODULE 1.3 ALOE Architecture
8. ALOE Webinar. May 24th 2012. http://flexnets.upc.edu/ m1 m2 m3 m4 m5 m1 m2 m1 m2 m1 m2 m3 m4 m5 m3 m4 m5 m3 m4 m5 Processor 1 Processor 2 Internal Link External Link Module mapped to processor 1 Module mapped to processor 2 ALOE daemons timeslot x-1 timeslot x timeslot x+1 Stage 0 Stage 1 Stage 2 Stage 3 m1 m2 m3 m4 m5 m1 m1 m2 m2 m1 m1 m2 m2 m1 m1 m2 m2 m3 m4 m5 m3 m4 m5 m3 m4 m5 Processor 1 Processor 2 Internal Link External Link Module mapped to processor 1 Module mapped to processor 2 ALOE daemons timeslot x-1 timeslot x timeslot x+1 Stage 0 Stage 1 Stage 2 Stage 3 ADC fs Rate Conv. fs ' 1.4 ALOE Time Management  Time slots synchronized to ADC/DAC  Cooperative, static scheduling  Relaxed synchronization  Deterministic latency
9. 2. Computing Resource Management MODELING MANAGEMENT
10. C = (C1 , C2 , C3 ) MOPTS B = MBPTS  Processing resources and requirements  Inter-processor bandwidth resources and requirements Example: SDR Platform Model MOPTS Million operations per time slot MBPTS Mega-bits per time slot • Abstraction layers provide computing resources & requirements in above units • Availability of software modules for each processor type processor-internal bandwidths C 2 C 3 C 1 B P 3 P 1 P 2 C 2 C 3 C 1 B C 2 C 2 C 3 C 3 C 1 C 1 B P 3 P 1 P 2 B B B B B B 2.1 SDR Platform Modeling
11. DDS Sampling Rate Frequency Adjust Ray Search 2450 MOPS 492 MOPS 120 MOPS 130 MOPS 1 MOPS Interpolator Decimator 46 MOPS 492 MOPS 2450 MOPS 160 MOPS 4-Finger RAKE MRC Channel Estimation 92 MOPS DPCH f= 1 KHz fs = 61.44 MHz 4·4000 MOPS Maximum Search Sync2 Sync1 Sync1 Sync4 Sync3 fs = 65 MHz 2nd Deinter- leaving CRC Physical Channel De- Mapping Physical Channel Deseg- mentation 10 MOPS Radio Frame Deseg- mentation 62.9 MOPS 1st Deinter- leaving 116 MOPS Rate Match- ing 141 MOPS Turbo De- coding 342 MOPS TrBk Concat./ CodeBk Deseg. 11.7 MOPS 0.2 MOPS 0.384 Mbps 1.15 Mbps 10 MOPS 105 MOPS 4 Matched Filter 3.84 MHz 15.36 MOPS 4 Sampling Rate Matched Filter fs = 15.36 MHz fs = 3.84 MHz 7.68 Mbps Chip Sync 2.2 Waveform: UMTS Downlink Receiver
12. 289·10-3 76.5·10-3 0.578 0.578 72·10-3 677·10-6 226·10-6 677·10-6 677·10-6 27·10-3 588·10-6 54.1·10-3 5.88·10-3 5.88·10-3 37·10-3 68.2·10-3 82.9·10-3 201·10-3 6.88·10-3 118·10-6 4.5·10-3 94.1·10-3 61.8·10-3 226·10-6 9.4·10-6 70.6·10-3 4.5·10-3 9.04·10-3 72·10-3 289·10-3 2.35 2.35 2.35 2.35 f9 f8 f7 f6 f3 f2 f1 f11 f13 f12 f14 f15 f16 f17 f18 f19 f20 f21 f22 1.44 1.44 f23 f24 f10 f4 f5 9.4·10-6 36·10-3 0.145 (a) c= (0.076, 0.289, 0.289, 1.44, 1.44, 2.35, 2.35, …) MOPTS con = 0.12 b= MBPTS              0 0 0 0 0 0 145 . 0 0 0 0 0 0 145 . 0 0 0 0 0 0 0 578 . 0 0 0 0 0 0 0 578 . 0 0 0 0 0 0 0 612 . 0 612 . 0 0 s= (1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 6, 6, 7, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17) Function model: Dataflow model: Stage model: cT = 13.675 MOPTS 2.3 SDR Application Modeling MOPTS MBPTS Time slot: 0.6 ms
13. ALOE Webinar. May 24th 2012. http://flexnets.upc.edu/  Dynamic programming  Parameter w controls algorithm complexity  Cost function independent  control different resources  define different optimization goals Two-term cost function: 2.4 The tw -mapping & Cost Function processing requirement available processing power bandwidth requirement available bandwidth + balance processing load minimize data flows Cost = V. Marojevic, “Computing Resource Management in Software-Defined and Cognitive Radios,” doctoral dissertation, Dept. Signal Theory and Communications, UPC, 2009.
14. ALOE Webinar. May 24th 2012. http://flexnets.upc.edu/ 17 {P1 , fi } represents the mapping of waveform component fi to processor P1 Processors P 1 P 2 P 3 f i – 1 f i f i +1 f i + w – 2 f i+ w – 1 … window size w origin reference decision Waveform modules 2.4 The tw -mapping & Cost Function
15. ALOE Webinar. May 24th 2012. http://flexnets.upc.edu/ w = 1 f1 f2 f3 f4 0.5 0.6 P1 P2 Decision 1.2 2.4 The tw -mapping & Cost Function P1 P2 f1 f3 f4 0.5 0.6 Path costs 0.7 0.8 f1 , f2 , f4  P1 f3  P2 f1 f2 f3 f4 0.6 1.2 P1 P2 2 1.5 0.5 1.7 2.7 ∞ 2.7 f2 f2
16. • Development and Debugging Tools  ALOE lab sessions  Source code templates  Automatic code generation tools (Simulink Target)  Graphical user interface 3. ALOE Tools
17. Execution time statistics Execution control Parameter time evolution Loaded modules Schedule Module Output Parameter modification 3.1 Graphical User Interface (I)
18. 3.1 Graphical User Interface (II) Computing platform Processor loads Task schedule
19. 4. Waveform Development OFDM modulator OFDM demodulator Data Source CRC attachment Turbo encoder Interleaving Rate matching Mapping Pilot iFFT Cyclic DUC DDC Sync DeCyclic FFT Depilot & equalization Soft demapper Rate matching Interleaving CRC dettachment Sink DEMUX MUX Three bit streams Turbo decoder Turbo decoder Turbo decoder ▫ LTE-128 points. ▫ 1 MHz ▫ 3 bit-streams
20. DAC/ADC 4.1 Processing Platforms P1 P2 P4 P3 P1 P2 P4 P3 P5 P6 P8 P7 P9 P10 P12 P11 RF DAC/ADC RF i7 Quad-Core, 2,6 GHz ADC/DAC board: Innovative Integration X5-400 Sampling Rate: 61,44 MHz Time-slot: 2 ms. E2E-latency: 40 ms. GbE GbE GbE
21. DDC output Sync module output: Correlation with Zhou sequence 4.2 Signal Captures NOK OK Samples DA output (time and frequency domain)
22. ALOE Webinar. May 24th 2012. http://flexnets.upc.edu/ ALOE Project ▫ Open source framework for SDR ▫ Non-commercial research version ▫ Tested:  GPPs under Linux (x86 and ARM7)  DSPs under RTOS-BIOS (TMS C64xx)  UMTS bit-level, LTE (1 MHz) ▫ Documentation and downloads at http://flexnets.upc.edu/ 5. Summary