RISC-V CPU emulator made with Ruby

I talked at COSCUP x RubyConf Taiwan 2025

Transcript

1. RISC-V CPU emulator made with Ruby hachi 2025/08/09
2. 目次 • I’m Hachi • From Osaka Japan • Web application developer at freee • Co-founder of Kyobashi.rb • First time in Taiwan! Hayao Kimura (@hachiblog)
3. 目次 • I’m Hachi • From Osaka Japan • Web application developer at freee • Co-founder of Kyobashi.rb • First time in Taiwan! Hayao Kimura (@hachiblog)
4. 目次 • I’m Hachi • From Osaka Japan • Web application developer at freee • Co-founder of Kyobashi.rb • First time in Taiwan! Hayao Kimura (@hachiblog)
5. 目次 • I’m Hachi • From Osaka Japan • Web application developer at freee • First time in Taiwan! Hayao Kimura (@hachiblog) 腸粉
6. Why Ruby?🤔 Does it make sense to build this?
7. Please, just listen.
8. Key Takeaways from This Session • You can build a CPU emulator with ruby. • A CPU's basic implementation is surprisingly simple. • Ruby provides an accessible entry point for understanding hardware mechanisms, enabling easy CPU emulator creation and further exploration.
9. Agenda • Why I build it with Ruby • What specifically I built • Result
10. 技術書典18サークル応募
13. What if I made it a theme of learning basic information through practice?
14. Read a book for the Basic Information Technology Engineer Exam.
15. Why was two's complement better again?
16. Will I understand if I try to build it?
17. Let's build a CPU!
18. By the way...
20. Why Ruby?
21. Why Ruby? • Ruby is the language I'm most familiar with. • Ruby(interpreted languages) CPU emulators: uncommon
22. Prerequisite knowledge
23. What exactly is a CPU emulator?
24. General structure of a CPU Registers CPU Decoder ALU Memory Program Counter
25. First step: Instruction Fetch Registers CPU Decoder ALU Memory Program Counter 0x4c771663 0x800001a0
26. Registers CPU Decoder ALU Memory Program Counter Second step: Decode 0x4c771663
27. Registers CPU Decoder ALU Memory Program Counter Second step: Decode 0x34202f73 4c771663
28. Registers CPU Decoder ALU Memory Program Counter Second step: Decode 0x34202f73 4c771663 1001100011101110001011001100011
29. Registers CPU Decoder ALU Memory Program Counter Second step: Decode 0x34202f73 4c771663 1001100011101110001011001100011
30. Registers CPU Decoder ALU Memory Program Counter Second step: Decode 0x34202f73 4c771663 1001100011101110001011001100011 bne a4,t2,8000066c
31. Final step: execute Registers CPU Decoder ALU Memory Program Counter bne a4,t2,8000066c
32. Final step: execute Registers CPU Decoder ALU Memory Program Counter bne a4,t2,8000066c a4,t2
33. Final step: execute Registers CPU Decoder ALU Memory Program Counter bne a4,t2,8000066c a4,t2 8000066c
34. What is RISC-V • Open-source Instruction Set Architecture. • Adheres to the RISC (reduced instruction set computer) • Currently, fewer examples as PC CPUs; more common in microcontrollers and specific uses.
35. What is RISC-V • Open-source Instruction Set Architecture. • Adheres to the RISC (reduced instruction set computer) • Currently, fewer examples as PC CPUs; more common in microcontrollers and specific uses.
36. What is RISC-V • Open-source Instruction Set Architecture. • Adheres to the RISC (reduced instruction set computer) • Currently, fewer examples as PC CPUs; more common in microcontrollers and specific uses.
37. Scope of what we're building this time
38. Scope of what we're building this time Goal: Pass the add instruction test.
39. 今回作るもののスコープ add 命令テストが pass する
40. Implemented Instructions ADD ADDI LUI AUIPC Arithmetic SW Store JAL Jump & Link SLLI Shift ORI Logical ECALL Environment CSRRS CSRRW CSRRWI CSR BEQ BNE BLT Branch
41. Implementation Policy • Build basic Registers, Memory, Decoder. • Execute tests. • Raise exceptions for unimplemented instructions. ◦ Implement missing instructions. • Tests pass!
42. Implementation Structure • Create RISCV32CPU class. • Use load_program method to load program into memory. • Use execute method to run the program.
43. 実装
44. 実装
45. 実装
46. 実装
47. 実装
48. RISC-V Base Instruction Formats
53. “add a4, a1, a2” means “0x80000000 + 0xffff80000”
54. 0x80000000 + 0xffff80000 = 0x7fff8000 󰢏
55. 0x80000000 + 0xffff80000 = 0x7fff8000 󰢏 0x80000000 + 0xffff80000 = 0x17fff8000 󰢃
56. 󰢃 󰢏
58. -1 + -1 = -2 󰢏
59. -1 + -1 = -2 󰢏 -1 + -1 = 4294967294 󰢃
60. -1 + -1 = -2 󰢏
61. Implementation was successfully completed! 🎉
62. What I learned and how it felt • Ruby's ease allows web engineers (or anyone interested in underlying mechanisms) to grasp CPU fundamentals. • It provides an accessible entry point to understanding hardware mechanisms. • This implementation omitted complexities; logic circuit construction was largely abstracted by Ruby's power. • For deeper CPU interest, consider emulating logic circuits or using Hardware Description Languages (HDLs). • Ruby provides an accessible entry point, sparking further interest in computer mechanisms.
63. Why Ruby?🤔 Does it make sense to build this?
64. なんで Ruby で？ 作って意味ある？🤔 For me, it absolutely did!
65. Thank you for listening!