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Introduction of Technologies and People Supporting RISC-V Ecosystem

October 20, 2018

Introduction of Technologies and People Supporting RISC-V Ecosystem


October 20, 2018

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  1. Introduction of Technologies and People Supporting RISC-V Ecosystem RISC-Vエコシステムを構成する技術と立役者たち IEEE

    Micro51 RISC-V Day 2018 Fukuoka Saturday, October 20th 2018 09:45 - 10:00 FPGA Development Diary Author @msyksphinz_dev http://msyksphinz.hatenablog.com
  2. Self Introduction “FPGA Development Diary” www.msyksphinz.hatenablog.com “RISC-V Blogger” @msyksphinz_dev Writing

    about technical topics such as RISC-V, FPGA, CPU- architecture, Deep Learning, Quantum Computing... on my blog. My work: Hardware Development Engineer Designing processors, and debugging chips and so on... I am employed even though I write blog posts everyday. CQ publishing, “Interface” Magazine “Research of RISC-V, open-source instruction set architecture” series I don’t know how to pronounce that... APS-web.jp RISC-V for Beginners
  3. Introduction of technologies supporting RISC-V Eco-system • There are many

    technologies that support RISC-V • Software ecosystem • Hardware ecosystem • I will introduce various technologies, communities and tools.
  4. Goal of Open-Hardware including RISC-V • Building communities where hardware

    design and CPU architecture can be openly discussed. • Example: Meltdown / Spectre • Example: Memory Consistency Model of RISC-V • A RISC-V memory consistency model problem has been found by university researchers. • Security topics are mainly discussed in RISC-V community today. • Keystone: open security platform based on RISC-V. More people can join to develop More people can join to discuss hardware development entry barrier goes down. More people become hardware developers Expands the range of Hardware developers
  5. RISC-V open-source hardware / software is a chance for semiconductor

    industries • Mainstream CPU is x86 / Arm • But license fees are a problem while ever more money is required to use the latest process technology. • IP, EDA, Wafer manufacturing, packaging... • It is good to increase choices • We want to concentrate our “original” technologies, and reduce the effort for other parts (SoC, control CPU ...) • RISC-V is a good choice • Your own CPU core is hard to maintain only by yourself • GCC, Linux, toolchains, ... • Cutting costs by introducing RISC-V, including software ecosystem. • And RISC-V can solve the patent worries for your in-house developed CPU architecture. • Minimizing development cost of center of your SoC, the CPU • There are many other areas that require attention, not only the CPU. • We want to focus on the original and valuable parts in chips.
  6. People and technologies that support “RISC-V Instruction Set Architecture” RISC-V

    Foundation Working Group GCC Binutils LLVM Linux QEMU ISS BOOM Rocket- Chip Freedom SoC HiFive1 HiFive Unleashed Board and platform SIMD Extension Privileged Spec Security Memory model Software toolchain Board of directors mainly leads RISC-V ISA, and there are many Working groups for each sub-topic … Linux Package maintainer OS import by volunteer Maintenance by Foundation Member Maintenance by Foundation Member Board of Directors RISC-V ISA Manual
  7. Software Ecosystem ◼Almost all toolchains are finished to import ◼

    GCC 7.1 merged RISC-V into mainstream. ◼ LLVM/Clang RISC-V support is progressing, lead by the lowRISC project ◼ Linux Kernel merged from version 4.15 ◼ Linux Distributions RISC-V support progress ◼ RedHat / Debian ◼ FreeBSD : RISC-V support progress ◼ QEMU v2.12 supports build for RISC-V32/64 ◼ RISC-V test pattern identifies “what is RISC-V” ◼ We have to pass these test patterns. • riscv-tests (https://github.com/riscv/riscv-tests) • riscv-torture (https://github.com/ucb-bar/riscv-torture)
  8. Engineer communities supporting RISC-V • Anyone can join the RISC-V

    community • Google Groups(Mailing List) • You can get answers to various questions. Announcements Academic Community Software Developers Hardware Developers ISA Developers Debug • RISC-V Tags are prepared in Stack Overflow • SiFive Forum • Community for SiFive products and specifications. https://stackoverflow.com/questions/tagged/riscv https://forums.sifive.com https://riscv.org/mailing-lists/
  9. GitHub Repositories support RISC-V • Software Toolchains / Hardware Toolchains

    Note: SW/HW status is summarized at https://riscv.org/software-status, https://riscv.org/risc-v-cores/ riscv-tools riscv-openocd riscv-fesvr riscv-gnu-toolchain riscv-isa-sim riscv-opcodes riscv-tests riscv-pk OpenOCD for RISC-V Front-end server for RISC-V Simulation Compiler and Libraries Instruction Set Simulator RISC-V Test patterns RISC-V Proxy Kernel https://github.com/riscv/riscv-tools https://github.com/esperantotech/boom-template https://github.com/ucb-bar/project-template
  10. Hardware Ecosystem : Rocket-Chip/BOOM ZC706 ZedBoard Rocket-Chip BOOM Freedom-SoC HiFive1

    HiFive Unleashed ASIC 4+1Core RV64 1GHz Arduino RV32 320MHz FPGA AWS
  11. Power of RISC-V Open Ecosystem: Making RISC-V Simulator from scratch

    that can boot Linux • I want to understand RISC-V specification well. • I can’t understand by reading ISA manual only. Making RISC-V Simulator Target 1. Passing all test patterns Target 2. Boot Linux RISC-V Linux : Linux binary published at Freedom-U-SDK repository single Linux image built by buildroot. Kernel v4.15 Repository is at https://github.com/sifive/freedom-u-sdk Note: There are many open Linux distributions for RISC-V RedHat, Debian, ... This time, I’m using a single image version for simplicity.
  12. Power of RISC-V Open Ecosystem: Making RISC-V Simulator from scratch

    that can boot Linux pk (proxy kernel) RISC-V Instruction Set Simulator dtb Device Tree Blob Target Program Elf Log Files x86 Host Linux Reference materials Note: pk(proxy kernel) Structures to handle system calls in place of the actual RISC-V It can pass on system calls such as printf() and file-system access on to the x86 host machine Note: PK is not used for booting Linux RISC-V ISA Spec Manual RISC-V Privileged Manual Implementation of riscv-isa-sim It is recommended to look into the simulator when you can't understand by only reading the manual. It faithfully reproduces the RISC-V spec by C++. GitHub address : http://github.com/msyksphinz/swimmer_riscv RISC-V Implementation reads device tree at initial phase of RISC-V boot
  13. RISC-V's great aspects I learned while booting Linux ◼ All

    tools are open, easy debugging ◼ https://github.com/riscv/riscv-tools ◼ Simple Instruction Set! ◼ All test patterns are open: ◼ ISA test pattern riscv-tests / riscv-torture ◼ I want to implement some functions → Anyway I can run regression test using riscv-tests to validate my implementation. ◼Test patterns for RISC-V ◼ RISC-V implementations should pass these tests. ◼ riscv-tests (https://github.com/riscv/riscv-tests) ◼ riscv-torture (https://github.com/ucb-bar/riscv-torture)
  14. • Try RISC-V by checking out an open source RISC-V

    core • You can start RISC-V even if you don’t have much money • Support for RISC-V ISA in hardware / software is steadily progressing. • Many ways to try RISC-V • Using FPGA Board : customize a design and run it on a FPGA. • Buy an evaluation board: evaluate your application easily. • Everyone has a chance! • If you can't find what you want, you and make it yourself and publish it on the internet. • Your contribution makes RISC-V community bigger. Summary: Everyone can join RISC-V communities If you are interested in RISC-V, You can join now. If more people join the effort, RISC-V will become more interesting.