RICH_graduate_presentation

Transcript

1. A Technique for Test Compression and Scan Chain Diagnosis Improvement AdvisorɿԦߦ݈ Sying-Jyan Wang Studentɿ௠ݐྑ Chien-Liang Chen  ϋ˜˚݋ಂɓ
2.  Abstract  Introduction  Proposed method  Experimental Results Outline  Previous work  ϋ˜˚݋ಂɓ
3. Outline Abstract Introduction Proposed method Experimental Results Previous work  ϋ˜˚݋ಂɓ
4. Abstract Introduction Proposed method Experimental Results Previous work  ϋ˜˚݋ಂɓ
5. Abstract  With the increased complexity of circuit, the test data volume and test time have become a critical issue.  We proposed a method that can improve not only test compression rate but help scan chain diagnosis.  The experimental results show that the test compression rate can achieve 2%-4% improvement.  And an average of 52%-56% improvement in diagnosis accuracy can be observed. Introduction Proposed method Experimental Results Previous work  ϋ˜˚݋ಂɓ
6. CUT ATE IO Channel  Test architecture:  Circuit Under Test, CUT  Automatic Test Equipment, ATE  IO Channel Test Pattern Test Response Abstract Introduction Proposed method Experimental Results Previous work  ϋ˜˚݋ಂɓ
7. Introduction CUT ATE IO Channel  Test architecture:  Circuit Under Test, CUT  Automatic Test Equipment, ATE  IO Channel Test Pattern Test Response Abstract Proposed method Experimental Results Previous work  ϋ˜˚݋ಂɓ
8.  Test Compression  Code-based scheme  Huffman code, run-length code, etc.  Linear-decompressor-based scheme  Linear Feedback Shift Register (LFSR)  Multiple Input Shift Register (MISR)  Broadcast-based scheme  can reduce both test time and test volume  Illinois Scan Architecture (ISA) Abstract Introduction Proposed method Experimental Results Previous work  ϋ˜˚݋ಂɓ
9.  Test Compression  Code-based scheme  Huffman code, run-length code, etc.  Linear-decompressor-based scheme  Linear Feedback Shift Register (LFSR)  Multiple Input Shift Register (MISR)  Broadcast-based scheme  can reduce both test time and test volume  Illinois Scan Architecture (ISA) Abstract Introduction Proposed method Experimental Results Previous Work  ϋ˜˚݋ಂɓ
10.  Broadcast-based scheme is widely used in multiple scan chains design. multiple scan chains architecture Abstract Introduction Proposed method Experimental Results Previous Work scan chain ATE ATE  ϋ˜˚݋ಂɓ
11.  Broadcast-based scheme is widely used in multiple scan chains design. multiple scan chains architecture Abstract Introduction Proposed method Experimental Results Previous Work scan chain ATE ATE scan chain scan chain  ϋ˜˚݋ಂɓ
12.  Broadcast-based scheme is widely used in multiple scan chains design. multiple scan chains architecture Abstract Introduction Proposed method Experimental Results Previous Work scan chain ATE ATE scan chain scan chain decompressor compactor  ϋ˜˚݋ಂɓ
13.  Illinois Scan Architecture (ISA) νྡɧהͪdISA ึਗ਼ɓૢધ౜ᗡʱϓεࡈ༰೵ٙધ౜ਜݬ(scan segment)d຅ધ౜ਜݬගٙ༟ࣘ־Ϥ޴࢙dۆהϞٙધ౜ਜݬఱึ৔ ආ޴Νٙ࠽f Segment 1 Segment 2 Segment 3 Segment 4 Scan-in Output Compression ྡ ɧjͺлፕધ౜ݖ࿴ Abstract Introduction Proposed method Experimental Results Previous Work segment 1: 0 X X segment 2: X X 1 segment 3: 1 X X segment 4: X 1 1 T1:0XXXX11XXX11 T2:1111XXX1XX11 segment 1: 1 1 1 segment 2: 1 X X segment 3: X 1 X segment 4: X 1 1 conflict compatible output compactor slice  ϋ˜˚݋ಂɓ
14.  Multi-cast broadcast scan architecture [17] Abstract Introduction Proposed method Experimental Results Previous Work [17] P.-C. Tsai and S.-J. Wang, “Multi-mode-segmented scan architecture with layout-aware scan chain routing for test data and test time reduction,” IEEE Computers & Digital Techniques, IET, vol. 2, pp. 434-444, 2008.  ϋ˜˚݋ಂɓ
15.  Multi-cast broadcast scan architecture [17] Scan Chain 1 Scan Chain 2 Scan Chain 3 Scan Chain 4 Scan Chain 5 Scan Chain 6 configuration 1 Abstract Introduction Proposed method Experimental Results Previous Work [17] P.-C. Tsai and S.-J. Wang, “Multi-mode-segmented scan architecture with layout-aware scan chain routing for test data and test time reduction,” IEEE Computers & Digital Techniques, IET, vol. 2, pp. 434-444, 2008.  ϋ˜˚݋ಂɓ
16.  Multi-cast broadcast scan architecture [17] Scan Chain 1 Scan Chain 2 Scan Chain 3 Scan Chain 4 Scan Chain 5 Scan Chain 6 configuration 1 Abstract Introduction Proposed method Experimental Results Previous Work [17] P.-C. Tsai and S.-J. Wang, “Multi-mode-segmented scan architecture with layout-aware scan chain routing for test data and test time reduction,” IEEE Computers & Digital Techniques, IET, vol. 2, pp. 434-444, 2008.  ϋ˜˚݋ಂɓ
17.  Multi-cast broadcast scan architecture [17] Scan Chain 1 Scan Chain 2 Scan Chain 3 Scan Chain 4 Scan Chain 5 Scan Chain 6 configuration 1 Abstract Introduction Proposed method Experimental Results Previous Work [17] P.-C. Tsai and S.-J. Wang, “Multi-mode-segmented scan architecture with layout-aware scan chain routing for test data and test time reduction,” IEEE Computers & Digital Techniques, IET, vol. 2, pp. 434-444, 2008.  ϋ˜˚݋ಂɓ
18.  Multi-cast broadcast scan architecture [17] Scan Chain 1 Scan Chain 2 Scan Chain 3 Scan Chain 4 Scan Chain 5 Scan Chain 6 Scan Chain 1 Scan Chain 2 Scan Chain 3 Scan Chain 4 Scan Chain 5 Scan Chain 6 configuration 1 configuration 2 Abstract Introduction Proposed method Experimental Results Previous Work [17] P.-C. Tsai and S.-J. Wang, “Multi-mode-segmented scan architecture with layout-aware scan chain routing for test data and test time reduction,” IEEE Computers & Digital Techniques, IET, vol. 2, pp. 434-444, 2008.  ϋ˜˚݋ಂɓ
19.  Multi-cast broadcast scan architecture [17] Scan Chain 1 Scan Chain 2 Scan Chain 3 Scan Chain 4 Scan Chain 5 Scan Chain 6 Scan Chain 1 Scan Chain 2 Scan Chain 3 Scan Chain 4 Scan Chain 5 Scan Chain 6 configuration 1 configuration 2 Abstract Introduction Proposed method Experimental Results Previous Work [17] P.-C. Tsai and S.-J. Wang, “Multi-mode-segmented scan architecture with layout-aware scan chain routing for test data and test time reduction,” IEEE Computers & Digital Techniques, IET, vol. 2, pp. 434-444, 2008.  ϋ˜˚݋ಂɓ
20.  Multi-cast broadcast scan architecture [17] Scan Chain 1 Scan Chain 2 Scan Chain 3 Scan Chain 4 Scan Chain 5 Scan Chain 6 Scan Chain 1 Scan Chain 2 Scan Chain 3 Scan Chain 4 Scan Chain 5 Scan Chain 6 configuration 1 configuration 2 Abstract Introduction Proposed method Experimental Results Previous Work [17] P.-C. Tsai and S.-J. Wang, “Multi-mode-segmented scan architecture with layout-aware scan chain routing for test data and test time reduction,” IEEE Computers & Digital Techniques, IET, vol. 2, pp. 434-444, 2008.  ϋ˜˚݋ಂɓ
21.  Diagnosis  Combinational Logic Circuit Diagnosis  Scan Chain Diagnosis  Scan Chain Diagnosis  achieves higher yield and aids in silicon debug  [1] indicates scan chains can occupy nearly 30% of a chip’s area, and chain failures account for almost 50% of chip failures.  Therefore, scan chain failure diagnosis is important to scan-based testing. [1] S. Kundu, “On diagnosis of faults in a scan-chain,” in Proc. VLSI Test Symp., pp. 303-308, Apr. 1993. Abstract Introduction Proposed method Experimental Results Previous Work  ϋ˜˚݋ಂɓ
22.  Scan Chain Diagnosis  Tester-based diagnosis  use tester to control scan chain shift operations, and physical failure analysis(PFA) equipment to observe defective location.  Hardware-based diagnosis  Software-based diagnosis Abstract Introduction Proposed method Experimental Results Previous Work  ϋ˜˚݋ಂɓ
23.  Hardware-based diagnosis  uses special scan chain and scan cell design to make the diagnosis process more effective. Abstract Introduction Proposed method Experimental Results Previous Work [24] Y. Wu, “Diagnosis of scan chain failures,” in Proc. Defect and Fault Tolerance in VLSI Systems, pp. 217-222, Nov. 1998.  ϋ˜˚݋ಂɓ
24.  Hardware-based diagnosis  uses special scan chain and scan cell design to make the diagnosis process more effective. Abstract Introduction Proposed method Experimental Results Previous Work = 1 the state of each flip-flop inverts as the secon 0 again and assume the inverted state stays. Now cycles it takes to observe the first 1 at the scan out this case, the first 1 is observed at the 3rd clock, fault but flip-flop 3 has not. In other words, the fa input, which corresponds to the assumed fault loc FIGURE 4. Fault diagnosis by flipping scan flops. Figure 5 shows a logical representation o state when dm (diagnostic mode) is set to 1. Wh normal scan flip-flop with an extra mux delay add 2 3 4 5 clk diag 1 (a) a scan chain of five flops sa1 after a ( si q si q si q si q si q dm dm dm dm dm  [24] adds inverse control signal [24] Y. Wu, “Diagnosis of scan chain failures,” in Proc. Defect and Fault Tolerance in VLSI Systems, pp. 217-222, Nov. 1998.  ϋ˜˚݋ಂɓ
25.  Hardware-based diagnosis  uses special scan chain and scan cell design to make the diagnosis process more effective. Abstract Introduction Proposed method Experimental Results Previous Work = 1 the state of each flip-flop inverts as the secon 0 again and assume the inverted state stays. Now cycles it takes to observe the first 1 at the scan out this case, the first 1 is observed at the 3rd clock, fault but flip-flop 3 has not. In other words, the fa input, which corresponds to the assumed fault loc FIGURE 4. Fault diagnosis by flipping scan flops. Figure 5 shows a logical representation o state when dm (diagnostic mode) is set to 1. Wh normal scan flip-flop with an extra mux delay add 2 3 4 5 clk diag 1 (a) a scan chain of five flops sa1 after a ( si q si q si q si q si q dm dm dm dm dm  [24] adds inverse control signal [24] Y. Wu, “Diagnosis of scan chain failures,” in Proc. Defect and Fault Tolerance in VLSI Systems, pp. 217-222, Nov. 1998. 00000  ϋ˜˚݋ಂɓ
26.  Hardware-based diagnosis  uses special scan chain and scan cell design to make the diagnosis process more effective. Abstract Introduction Proposed method Experimental Results Previous Work = 1 the state of each flip-flop inverts as the secon 0 again and assume the inverted state stays. Now cycles it takes to observe the first 1 at the scan out this case, the first 1 is observed at the 3rd clock, fault but flip-flop 3 has not. In other words, the fa input, which corresponds to the assumed fault loc FIGURE 4. Fault diagnosis by flipping scan flops. Figure 5 shows a logical representation o state when dm (diagnostic mode) is set to 1. Wh normal scan flip-flop with an extra mux delay add 2 3 4 5 clk diag 1 (a) a scan chain of five flops sa1 after a ( si q si q si q si q si q dm dm dm dm dm  [24] adds inverse control signal [24] Y. Wu, “Diagnosis of scan chain failures,” in Proc. Defect and Fault Tolerance in VLSI Systems, pp. 217-222, Nov. 1998. 00000 0 0 1 1 1  ϋ˜˚݋ಂɓ
27.  Hardware-based diagnosis  uses special scan chain and scan cell design to make the diagnosis process more effective. Abstract Introduction Proposed method Experimental Results Previous Work = 1 the state of each flip-flop inverts as the secon 0 again and assume the inverted state stays. Now cycles it takes to observe the first 1 at the scan out this case, the first 1 is observed at the 3rd clock, fault but flip-flop 3 has not. In other words, the fa input, which corresponds to the assumed fault loc FIGURE 4. Fault diagnosis by flipping scan flops. Figure 5 shows a logical representation o state when dm (diagnostic mode) is set to 1. Wh normal scan flip-flop with an extra mux delay add 2 3 4 5 clk diag 1 (a) a scan chain of five flops sa1 after a ( si q si q si q si q si q dm dm dm dm dm  [24] adds inverse control signal [24] Y. Wu, “Diagnosis of scan chain failures,” in Proc. Defect and Fault Tolerance in VLSI Systems, pp. 217-222, Nov. 1998. 00000 1 1 0 0 0  ϋ˜˚݋ಂɓ
28.  Hardware-based diagnosis  uses special scan chain and scan cell design to make the diagnosis process more effective. Abstract Introduction Proposed method Experimental Results Previous Work  [23] each scan cell is connected to its “partner shift register” [24] Y. Wu, “Diagnosis of scan chain failures,” in Proc. Defect and Fault Tolerance in VLSI Systems, pp. 217-222, Nov. 1998. [23] J. L. Schafer, F. A. Policastri, and R. J. McNulty, “Partner SRLs for improved shift register diagnostics,” in Proc. VLSI Test Symp., pp. 198-201, Apr. 1992. 0 0 1 1 0 0 1 1  ϋ˜˚݋ಂɓ
29.  Software-based diagnosis  No hardware modification is required.  cause-effect: pre-calculate fault dictionary  effect-cause: fault injection and simulation Abstract Introduction Proposed method Experimental Results Previous Work  ϋ˜˚݋ಂɓ
30.  Effect-cause Scan Chain Diagnosis  Step 1: use chain pattern to find faulty chain and fault type  Step 2: get candidate list through software or hardware diagnosis solution  Step 3: After fault injection and simulation, compare CUD response with faulty response. If equaled, called perfect match. The location which get all perfect match are the diagnosis suspect. Abstract Introduction Proposed method Experimental Results Previous Work  ϋ˜˚݋ಂɓ
31.  Effect-cause Scan Chain Diagnosis  Step 1: use chain pattern to find faulty chain and fault type  Step 2: get candidate list through software or hardware diagnosis solution  Step 3: After fault injection and simulation, compare CUD response with faulty response. If equaled, called perfect match. The location which get all perfect match are the diagnosis suspect. Abstract Introduction Proposed method Experimental Results Previous Work Shift out Result 111111111111 Stuck at 1 000000000000 Stuck at 0 000100010001 Fast fall 001000100010 Slow rise 101110111011 Fast rise 011101110111 Slow fall shift out result when chain pattern: 001100110011  ϋ˜˚݋ಂɓ
32.  Effect-cause Scan Chain Diagnosis  Step 1: use chain pattern to find faulty chain and fault type  Step 2: get candidate list through software or hardware diagnosis solution  Step 3: After fault injection and simulation, compare CUD response with faulty response. If equaled, called perfect match. The location which get all perfect match are the diagnosis suspect. Abstract Introduction Proposed method Experimental Results Previous Work  ϋ˜˚݋ಂɓ
33.  Effect-cause Scan Chain Diagnosis  Step 1: use chain pattern to find faulty chain and fault type  Step 2: get candidate list through software or hardware diagnosis solution  Step 3: After fault injection and simulation, compare CUD response with faulty response. If equaled, called perfect match. The location which get all perfect match are the diagnosis suspect. Abstract Introduction Proposed method Experimental Results Previous Work [26]example stuck-at 1 X X X X X X X X expected value 1 X 1 0 0 1 1 1 observed value 1 1 1 1 1 1 0 1 scan input scan output LB UB [26] R. Guo and S. Venkataraman, “A technique for fault diagnosis of defects in scan chains,” in Proc. Int'l Test Conf., pp. 268-277, 2001.  [26]: full-masked pattern  ϋ˜˚݋ಂɓ
34. Abstract Introduction Proposed method Experimental Results Previous work  ϋ˜˚݋ಂɓ
35. Proposed method Abstract Introduction Experimental Results Previous work  ϋ˜˚݋ಂɓ
36.  Reconnect scan chain Proposed method Abstract Introduction Experimental Results Previous work  ϋ˜˚݋ಂɓ
37.  Reconnect scan chain Proposed method scan chain 1 scan chain 2 scan chain 3 scan chain 4 scan chain 5 scan chain 6 L Abstract Introduction Experimental Results Previous work  ϋ˜˚݋ಂɓ
38.  Reconnect scan chain Proposed method L/2 L/2 Abstract Introduction Experimental Results Previous work  ϋ˜˚݋ಂɓ
39.  Reconnect scan chain Proposed method L/2 L/2 Abstract Introduction Experimental Results Previous work  ϋ˜˚݋ಂɓ
40. Abstract Introduction Experimental Results Previous work Proposed method  ϋ˜˚݋ಂɓ
41. Perfect shuffle Inverse Abstract Introduction Experimental Results Previous work Proposed method  ϋ˜˚݋ಂɓ
42. Perfect shuffle Inverse Abstract Introduction Experimental Results Previous work Proposed method  ϋ˜˚݋ಂɓ
43. 1 2 3 4 5 6 7 8 9 10 Perfect shuffle Inverse Abstract Introduction Experimental Results Previous work Proposed method  ϋ˜˚݋ಂɓ
44. 1 2 3 4 5 6 7 8 9 10 Perfect shuffle Inverse Abstract Introduction Experimental Results Previous work Proposed method  ϋ˜˚݋ಂɓ
45. 1 2 3 4 5 6 7 8 9 10 Perfect shuffle Inverse Abstract Introduction Experimental Results Previous work Proposed method  ϋ˜˚݋ಂɓ
46. 1 2 3 4 5 6 7 8 9 10 Perfect shuffle Inverse Abstract Introduction Experimental Results Previous work Proposed method  ϋ˜˚݋ಂɓ
47. Perfect shuffle Inverse 1 2 3 4 5 6 7 8 9 10 Abstract Introduction Experimental Results Previous work Proposed method  ϋ˜˚݋ಂɓ
48. Perfect shuffle Inverse 1 2 3 4 5 6 7 8 9 10 Abstract Introduction Experimental Results Previous work Proposed method  ϋ˜˚݋ಂɓ
49. Perfect shuffle Inverse 1 2 3 4 5 6 7 8 9 10 Abstract Introduction Experimental Results Previous work Proposed method 1-h 1-t 2-h 2-t 3-h 3-t 4-h 4-t 5-h 5-t 6-h 6-t 1-h 1-t 2-h 2-t 3-h 3-t 4-h 4-t 5-h 5-t 6-h 6-t  ϋ˜˚݋ಂɓ
50. Perfect shuffle Inverse 1 2 3 4 5 6 7 8 9 10 Abstract Introduction Experimental Results Previous work Proposed method 1-h 1-t 2-h 2-t 3-h 3-t 4-h 4-t 5-h 5-t 6-h 6-t 1-h 1-t 2-h 2-t 3-h 3-t 4-h 4-t 5-h 5-t 6-h 6-t 1-h 1-t 2-h 2-t 3-h 3-t 4-h 4-t 5-h 5-t 6-h 6-t 1-h 1-t 2-h 2-t 3-h 3-t 4-h 4-t 5-h 5-t 6-h 6-t  ϋ˜˚݋ಂɓ
51.  Broadcast flow ATPG pattern Broadcast check Multicast check Reconnection mode check Serial mode Start All pattern checked? X-filling and test compaction End yes Broadcast mode Multicast mode Reconnection mode no no no yes yes yes no Abstract Introduction Experimental Results Previous work Proposed method  ϋ˜˚݋ಂɓ
52. mode 1, m1 mode 2, m2 Abstract Introduction Experimental Results Previous work Proposed method  ϋ˜˚݋ಂɓ
53.  scan chain diagnosis  step 1: Using chain pattern to find fault type and faulty chain.  step 2: According the fault position(head/tail portion), analysis the simulation result.  step 3: Traceback and rank suspect from candidate list. Abstract Introduction Experimental Results Previous work Proposed method  ϋ˜˚݋ಂɓ
54.  fault in the head portion  load in two connection modes  unload in one connection mode X s1 s2 s3 s4 X s1 s2 s3 s4 X s1 s2 s3 s4 X s1 s2 s3 s4 simulate load unload Abstract Introduction Experimental Results Previous work Proposed method  ϋ˜˚݋ಂɓ
55. X s1 s2 s3 s4 X s1 s2 s3 s4 X s1 s2 s3 s4 simulate  fault in the tail portion  load in one connection mode  unload in two connection modes X s1 s2 s3 s4 load unload Abstract Introduction Experimental Results Previous work Proposed method  ϋ˜˚݋ಂɓ
56.  Diagnosis flow Start ATPG pattern All pattern simulate? Find fault type and faulty chain End shift in using the first connection mode and simulate ATPG pattern shift in using the first connection mode and simulate All pattern simulate? trace back and find candidates shift in using the second connection mode and simulate trace back and find candidates merge first and second connection mode output trace back and find candidates yes yes no faulty cell in the head of scan chain faulty cell in the tail of scan chain Rank candidates and find suspects no Abstract Introduction Experimental Results Previous work Proposed method  ϋ˜˚݋ಂɓ
57.  weighted backtrace combinational circuit 1 2 j n 1 2 b i n 1 2 b k b m b b b b b input cone output scan cells input scan cells primary output Abstract Introduction Experimental Results Previous work Proposed method  ϋ˜˚݋ಂɓ
58.  weighted backtrace combinational circuit 1 2 j n 1 2 b i n 1 2 b k b m b b b b b input cone output scan cells input scan cells primary output Abstract Introduction Experimental Results Previous work Proposed method #TSC(sci) is the number of scan cells in the input cone of error bit sci  ϋ˜˚݋ಂɓ
59.  weighted backtrace combinational circuit 1 2 j n 1 2 b i n 1 2 b k b m b b b b b input cone output scan cells input scan cells primary output Abstract Introduction Experimental Results Previous work Proposed method #TSC(sci) is the number of scan cells in the input cone of error bit sci  ϋ˜˚݋ಂɓ
60.  weighted backtrace combinational circuit 1 2 j n 1 2 b i n 1 2 b k b m b b b b b input cone output scan cells input scan cells primary output Abstract Introduction Experimental Results Previous work Proposed method #TSC(sci) is the number of scan cells in the input cone of error bit sci  ϋ˜˚݋ಂɓ
61. Abstract Introduction Experimental Results Previous work Proposed method  weighted backtrace ! b ! ! ! c d e a b c d e a b c d e a T1 T2 b c d e a  ϋ˜˚݋ಂɓ
62. Abstract Introduction Experimental Results Previous work Proposed method  weighted backtrace ! b ! ! 1/3 1/3 1/3 ! c d e a b c d e a b c d e a :1/3 :1/3 :1/3 T1 T2 b c d e a  ϋ˜˚݋ಂɓ
63. Abstract Introduction Experimental Results Previous work Proposed method  weighted backtrace ! b ! ! ! c d e a b c d e a b c d e a :1/3 :1/3 :1/3 T1 T2 1 1 +1 :1 b c d e a  ϋ˜˚݋ಂɓ
64. Abstract Introduction Experimental Results Previous work Proposed method  weighted backtrace ! b ! ! ! 1/4 1/4 1/4 1/4 c d e a b c d e a b c d e a :1/3 :1/3 :1/3 T1 T2 +1 :1 +1/4 +1/4 +1/4 :1/4 b c d e a  ϋ˜˚݋ಂɓ
65. Abstract Introduction Experimental Results Previous work Proposed method  weighted backtrace ! b ! ! ! c d e a b c d e a b c d e a :1/3 :1/3 :1/3 T1 T2 +1 :1 +1/2 +1/2 +1/4 +1/4 +1/4 :1/4 1/2 1/2 b c d e a  ϋ˜˚݋ಂɓ
66. Abstract Introduction Experimental Results Previous work Proposed method  weighted backtrace ! b ! ! ! c d e a b c d e a b c d e a :1/3 :1/3 :1/3 T1 T2 +1 :1 +1/2 +1/2 +1/4 +1/4 +1/4 :1/4 1/2 1/2 =1/3 =19/12 =7/12 =7/4 =3/4 b c d e a  ϋ˜˚݋ಂɓ
67. Abstract Introduction Experimental Results Previous work Proposed method  weighted backtrace ! b ! ! ! c d e a b c d e a b c d e a :1/3 :1/3 :1/3 T1 T2 +1 :1 +1/2 +1/2 +1/4 +1/4 +1/4 :1/4 1/2 1/2 =1/3 =19/12 =7/12 =7/4 =3/4 b c d e a d→b→e→c→a  ϋ˜˚݋ಂɓ
68. Abstract Introduction Proposed method Experimental Results Previous work  ϋ˜˚݋ಂɓ
69. Experimental Results  Benchmark: ISCAS’89 and ITC’99  Test patterns generation: Atalanta ATPG [2]  Fault simulation: HOPE [3] [2] H. K. Lee and D. S. Ha, “An efficient, forward fault simulation algorithm based on the parallel pattern single fault propagate,” in Proc. Int'l Test Conf., p. 946, 26-30 Oct. 1991. [3] H. K. Lee and D. S. Ha, “HOPE: an efficient parallel fault simulator for synchronous sequential circuits,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 15, pp. 1048-1058, 1996. Abstract Introduction Proposed method Previous work  ϋ˜˚݋ಂɓ
70. Experimental Results circuit name # of cell # of gate Length Length fault coverage (%) circuit name # of cell # of gate chain=10 chain=30 fault coverage (%) s5378 214 2779 22 8 99.131 s9234 247 5597 25 9 93.475 s13207 700 7951 70 24 98.462 s15850 611 9772 62 21 96.682 s35932 1763 16065 176 9 89.809 s38417 1664 22179 167 56 99.471 s38584.1 1464 19253 147 49 95.852 b14 277 9767 28 10 99.228 b17 1452 30777 146 49 80.275 b20 522 19682 53 18 95.486 b21 522 20027 53 18 89.232 b22 767 29162 77 26 90.722 •benchmark information Abstract Introduction Proposed method Previous work  ϋ˜˚݋ಂɓ
71. Experimental Results benchmark # of broadcast # of multicast # of reconnectio n # of serial improve ment(%) s9234 187 228 11 110 2 s35932 63 16 0 11 0 s38584.1 613 141 0 44 0 s38417 901 70 0 0 0 b14 648 360 28 19 3 b17 1090 512 139 52 8 b22 868 627 102 29 6 b21 849 324 67 200 5 b20 845 261 32 224 2 s15850 334 170 13 40 2 s13207 303 203 1 40 0 s5378 191 123 0 6 0 average - - - - 2 • broadcast with 10 scan chains Abstract Introduction Proposed method Previous work  ϋ˜˚݋ಂɓ
72. Experimental Results benchmark # of broadcast # of multicast # of reconnection # of serial improve ment(%) s9234 66 186 12 285 2 s35932 54 30 0 18 0 s38584.1 519 414 11 163 1 s38417 822 206 0 40 0 b14 109 611 82 488 6 b17 905 505 199 165 11 b22 922 666 110 42 6 b21 882 655 77 25 5 b20 848 640 54 190 3 s15850 161 270 40 154 6 s13207 152 360 5 101 1 s5378 64 192 13 98 4 average - - - - 4 • broadcast with 30 scan chains Abstract Introduction Proposed method Previous work  ϋ˜˚݋ಂɓ
73. Experimental Results circuit name original (without reconfiguration) original (without reconfiguration) original (without reconfiguration) reconnection (unweighted) reconnection (unweighted) reconnection (unweighted) improv- ement circuit name rank same score total rank same score total improv- ement s5378 7.75 0.95 8.7 4.08 0.66 4.74 45.52% s9234 9.13 0.37 9.5 5.02 0.13 5.15 45.79% s13207 25.81 0.33 26.14 12.53 0.14 12.67 51.53% s35932 64.68 6.43 71.11 29.41 1.65 31.06 56.32% s38417 71.8 14.58 86.38 37.42 4.37 41.79 51.63% s38584.1 65.05 0.4 65.45 29.73 0.1 29.83 54.42% b14 10.45 1.4 11.85 5.44 0.39 5.83 50.80% b17 56.8 32.98 89.78 27.97 14.74 42.71 52.43% b22 30.97 16.4 47.37 16.06 3.87 19.93 57.93% b21 20.57 10.06 30.63 11.48 2.84 14.32 53.25% b20 21.6 8.12 29.72 11.54 1.47 13.01 56.22% average - - - - - - 52.35% • diagnosis result with reconnection Abstract Introduction Proposed method Previous work  ϋ˜˚݋ಂɓ
74. Experimental Results Circuit name Original (without reconnection) Original (without reconnection) Original (without reconnection) Weighted backtrace Weighted backtrace Weighted backtrace Improvement Circuit name Rank Same score total Rank Same score total Improvement s5378 7.75 0.95 8.7 3.82 0.26 4.08 53.10% s9234 9.13 0.37 9.5 4.86 0.11 4.97 47.68% s13207 25.81 0.33 26.14 12.98 0.05 13.03 50.15% s35932 64.68 6.43 71.11 26.86 1.04 27.9 60.77% s38417 71.8 14.58 86.38 34.51 2.83 37.34 56.77% s38584.1 65.05 0.4 65.45 27.74 0.03 27.27 58.33% b14 10.45 1.4 11.85 4.89 0.06 4.95 58.23% b17 56.8 32.98 89.78 29.35 10.14 39.49 56.01% b22 30.97 16.4 47.37 17.56 0.06 17.62 62.8% b21 20.57 10.06 30.63 12.76 0.01 12.77 58.31% b20 21.6 8.12 29.72 11.74 0.07 11.81 60.26% average - - - - - - 56.58% •diagnosis result with weighted backtrace Abstract Introduction Proposed method Previous work  ϋ˜˚݋ಂɓ
75. Thanks for attention!  ϋ˜˚݋ಂɓ