SECRETS *Planned/projected performance Tensix Cores DRAM Cores ETH Cores PCIe Core ARC Core T D E P A CPU RISC-V CPUs コア数/SRAM容量: 1.75倍 動作周波数: 1.35倍 Compute: 2.65倍 DRAM容量: 2.7倍 帯域: 1.7倍 Ethernet帯域: 3倍 消費電力: 2~3倍!! TensixCoreの配置が変わる →Tileレベル最適化はやり直し
64 • Tensix Core – FPU uses ~85% of power Multiple Data Formats Supported • FP8/16/32, BFLOAT16, BLOCKFP2/4/8, INT8/32, TF32 General Purpose SIMD Engine (SFPU) • Fast transcendental instructions • Gelu, exponential, softmax • SFPU C++ compiler • No need to off-load to CPU CONFIDENTIAL - CONTAINS TRADE SECRETS Tensix-BH Features: 基本的にWHと同じ Silicon-Proven with Tenstorrent Galaxy, Wormhole , and Blackhole
• Can be connected into any topology • Mesh topology is great for AI • Locality and regularity of data movement • Sharded data • 200 GB/s in N / S / W / E / Z • 2D / 3D torus 10 T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T C C C C C C C C C C C C C C C C E E E E E E E E DRAM T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T C C C C C C C C C C C C C C C C E E E E E E E E DRAM T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T C C C C C C C C C C C C C C C C E E E E E E E E DRAM T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T C C C C C C C C C C C C C C C C E E E E E E E E DRAM E E E E E E E E Tile Math Engine RISC-V Router DRAM Bank Controller ETH Controller Vector Math Engine Compute Data Movement Storage RISC-V RISC-V RISC-V RISC-V user kernel user kernel user kernel user kernel user kernel