Heterodyning Non Destructive Testing electronic system based on eddy currents

Master thesis dissertation presentation presented on 19th November 2013 at Instituto Superior Técnico, Oeiras, Portugal

Transcript

1. Heterodyning  Non  Destruc1ve  Tes1ng   Electronic  System     Based  on  Eddy  Currents     Master’s  Degree  Disserta1on   Electronics  Engineering     Diogo  Elói  Trindade  de  Aguiam   Tuesday,  November  19,  2013  
2. Introduc1on   §  What  is  Non  Destruc0ve  Tes0ng?   –  “Analysis  techniques  used  in  science  and  industry  to   evaluate  the  proper5es  of  a  material,  component  or   system  without  causing  damage.”   –   Cartz,  Louis  (1995).  Nondestruc0ve  Tes0ng.  A  S  M  Interna0onal.       –  NDT  techniques:   •  Ultrasonic;   •  Magne0c  par0cles;   •  Radiographic;   •  Eddy  currents…   November  19,  2013   2  
3. Eddy  Currents  Phenomenon   November  19,  2013   3  
4. Eddy  Currents  Phenomenon   November  19,  2013   4  
5. Eddy  Currents  Probes   November  19,  2013   5   ! Sensitive Coils Shielding Plane PCB Substrate Driver Trace ! Driver Trace Terminals Pickup Coils Probe  A   •  10  mm  sensi0ve  area  diameter   •  10  windings  per  coil   •  Higher  sensi0vity   Probe  B   •  5  mm  sensi0ve  area  diameter   •  4  windings  per  coil   •  Higher  resolu0on  
6. Eddy  Currents  Inspec1on   §  Fric0on  S0r  Welding  Inspec0on   November  19,  2013   6  
7. Original  Valida1on  System   November  19,  2013   7  
8. Objec1ves   §  Develop  an  eddy  currents  NDT  electronic  system:   –  Compa0ble  with  the  developed  probe;   –  Applying  heterodyning  techniques  in  the  analog  front-­‐end;   –  Versa0lity  of  opera0on:   •  10  kHz  to  10  MHz  excita0on  frequency;   •  100  mA,  200  mA,  500  mA  and  1  A  pk-­‐pk  excita0on  current  scales;   •  Programmable  gain  amplifica0on  chain;   –  USB  2.0  High-­‐Speed  communica0on  with  a  host  computer.   –  LabVIEW  interface  for  inspec0on  configura0on  and   visualiza0on  of  results;   –  Installa0on  inside  a  portable  computer.   November  19,  2013   8  
9. Digital Domain ADC A A Probe Response cos(t) Real (n) Imaginary (n) ADC B sin(t) DDS B DDS A DRV 1 A/V Probe Excitation fexcitation fexcitation Opera1on  Modes   §  Direct  conversion  or  zero-­‐IF  mode   November  19,  2013   9   1  MHz   1  MHz   1  MHz   DC  +  2  MHz   DC  +  2  MHz   DC   DC   DC   DC  
10. Digital Processing ADC A Probe Response sample(n) cos(n) sin(n) Low-Pass Digital Filters Real(n) Imaginary(n) A DDS A Reference Clock DRV Probe Excitation DDS B 1 A/V fIF fexcitation fexcitation - fIF fIF fIF fexcitation Opera1on  Modes   §  Intermediate  frequency  mode   November  19,  2013   10   1  MHz   1  kHz  +     1999  kHz   DC   1  MHz   1  kHz   999  kHz   1  kHz   1  kHz   1  kHz   DC  +   2  kHz   DC  +   2  kHz   DC  
11. System  Architecture   November  19,  2013   11   Amplification Chain Sinusoidal Oscillator Downconversion & Acquisition DSP ADC A PGA FIFO to USB Power Motion Control ADC B SPI DDS B DDS A DAC AD7685 AD7685 AD9851 AD835 AD835 AD5621 AD8421 VCA821 AD9851 Probe Excitation CNV 16 6 -5 V +1.1 V +3.3 V +5 V +12 V ADSP-21489 SPI SPI SPI CLK X Stepper Motor Y Stepper Motor USB 2.0 Host 13 to 28 V Input Probe Response FT2232H L297 + L298 LOA LOB +ADJ V DRV 1 A/V Current Scale AD8061 Probe Excitation
12. Q1 FDT439N R1 R2A R2B R2C R2D C1 R3 R4 C2 +VDD/2 VIN + - VDD AD8041 ADG704 SCALE Q2 FDT434P D1 C4 C3 R5 R6 VDD VDD C5 C6 LSENSE 56 nH R8 R7 R9 RSENSE 0.5 Ω Probe R12 IOUT Probe Terminal Probe Terminal Input Buffering & Attenuator Input Stage Output Stage VSC R10 R11 R12 AD8061 +3.3 V + - Probe  Excita1on   November  19,  2013   12  
13. Probe  Driver  Frequency  Response   November  19,  2013   13   1 k 10 k 100 k 1 M 10 M −60 −40 −20 0 20 IO U T /IN O M [dB] Frequency [Hz] 1 A 500 mA 200 mA 100 mA Current Scale
14. Amplifica1on  and  Acquisi1on   November  19,  2013   14   Amplification Chain Downconversion & Acquisition ADC A PGA ADC B DAC AD7685 AD7685 AD835 AD835 AD5621 Differential Probe Response Probe 20 dB 20 dB VCA821 AD8421 AD8421 LOA LOB SDO SDI DATA CLK CNV DATA CLK CS Probe Terminals Pre-Amplifiers Gain Control Voltage +20 dB +40 dB
15. Amplifica1on  Frequency  Response   November  19,  2013   15   1k 10k 100k 1M 10M −40 −20 0 20 40 60 80 +20 dB +10 dB 0 dB −10 dB −20 dB Total Gain [dB] Frequency [Hz]
16. Direct  Conversion  Mode   November  19,  2013   16   Amplification Chain Downconversion & Acquisition ADC A PGA ADC B DAC AD7685 AD7685 AD835 AD835 AD5621 Differential Probe Response Probe 20 dB 20 dB VCA821 AD8421 AD8421 LOA LOB SDO SDI DATA CLK CNV DATA CLK CS Probe Terminals Pre-Amplifiers Gain Control Voltage +20 dB +40 dB
17. Intermediate  Frequency  Mode   November  19,  2013   17   Amplification Chain Downconversion & Acquisition ADC A PGA ADC B DAC AD7685 AD7685 AD835 AD835 AD5621 Differential Probe Response Probe 20 dB 20 dB VCA821 AD8421 AD8421 LOA LOB SDO SDI DATA CLK CNV DATA CLK CS Probe Terminals Pre-Amplifiers Gain Control Voltage +20 dB +40 dB
18. Digital  Signal  Processing   November  19,  2013   18   Digital Quadrature Demodulation Path A Path B x4 sample(n) Downconverted Probe Response x4 cos(n) sin(n) Digital LO Low-Pass IIR Filter Low-Pass IIR Filter Real (n) Imaginary (n) Buffer_B[n] Buffer_A[n] 1  kHz   DC  +   2  kHz   DC   1  kHz   DC   DC  +   2  kHz   DC   DC  
19. Prototype  Tes1ng  System   November  19,  2013   19   DSP Expansion Connectors Driver Circuit Amplification Chain Down- conversion Acquisition DDS Devices Connection to Host Computer Power Management USB
20. Prototype  Tes1ng  System   November  19,  2013   20   Probe   Connector   XY  Table   Connector   Reset   BuXon  
21. Control  Interface   November  19,  2013   21  
22. Prototype  Tes1ng  System   November  19,  2013   22  
23. Eddy  Currents  Valida1on   §  Mul0ple  Depth  Defects   November  19,  2013   23   0 10 20 30 40 50 60 70 80 0 1 2 3 4 5 6 7 X [mm] Amplitude U/I [mΩ] 100 kHz 1 MHz 10 MHz 0 10 20 30 40 50 60 70 80 0 2 4 6 8 10 X [mm] Amplitude U/I [mΩ] 100 kHz 1 MHz 10 MHz Probe  A  (10  mm)   Probe  B  (5  mm)  
24. Eddy  Currents  Valida1on   §  Double  defect   November  19,  2013   24   Probe  A  (10  mm)   Probe  B  (5  mm)   −5 −4 −3 −2 −1 0 1 2 3 4 5 0 50 100 150 X [mm] Amplitude U/I [mΩ] 100 kHz [x100] 1 MHz [x10] 10 MHz [x1] −5 −4 −3 −2 −1 0 1 2 3 4 5 0 5 10 15 20 25 X [mm] Amplitude U/I [mΩ] 100 kHz [x100] 1 MHz [x10] 10 MHz [x1]
25. Eddy  Currents  Valida1on   §  Ramp  depth  defect   November  19,  2013   25   Probe  A  (10  mm)   Probe  B  (5  mm)  
26. Eddy  Currents  Measurements   November  19,  2013   26   Machined Defect FSW Region 12 mm Regular FSW Inspection Defect Inspection X Y Z X Y Z −15 −10 −5 0 5 10 15 −0.04 −0.02 0 0.02 0.04 Real U/I [mΩ] X [mm] −15 −10 −5 0 5 10 15 −0.04 −0.02 0 0.02 0.04 0.06 Imaginary U/I [mΩ] X [mm] −15 −12.5 −10 −7.5 −5 −2.5 0 2.5 5 7.5 10 12.5 15 0 0.02 0.04 0.06 Amplitude U/I [mΩ] X [mm] Regular FSW FSW with Machined Defect −15 −10 −5 0 5 10 15 −0.04 −0.02 0 0.02 0.04 Real U/I [mΩ] X [mm] −15 −10 −5 0 5 10 15 −0.04 −0.02 0 0.02 0.04 0.06 Imaginary U/I [mΩ] X [mm] −15 −12.5 −10 −7.5 −5 −2.5 0 2.5 5 7.5 10 12.5 15 0 0.02 0.04 0.06 Amplitude U/I [mΩ] X [mm] Regular FSW FSW with Machined Defect −15 −10 −5 0 5 10 15 −0.04 −0.02 0 0.02 0.04 Real U/I [mΩ] X [mm] −15 −10 − −0.04 −0.02 0 0.02 0.04 0.06 Imaginary U/I [mΩ] −15 −12.5 −10 −7.5 −5 −2.5 0 2.5 5 0 0.02 0.04 0.06 Amplitude U/I [mΩ] X [mm]
27. §  The  heterodyning  techniques  on  the  analog  front-­‐ end  allowed  the  reduc0on  of  system  complexity.   §  The  reduced  system  footprint  allowed  its  installa0on   inside  a  portable  rugged  computer,  providing  a   standalone  instrument.   §  The  eddy  currents  NDT  system  was  validated  with   the  inspec0on  of  different  machined  defects.   §  FSW  defects  were  also  inspected  successfully.   Conclusions   November  19,  2013   27  
28. §  Develop  a  small  higher  sensi0vity  eddy  currents   probe;   §  Op0mize  the  analog  front-­‐end  for  heterodyning   direct  conversion;   §  Develop  a  new  mul0-­‐channel  NDT  system;   §  Develop  a  system  driver  to  allow  the  development  of   new  host  computer  interfaces.   Future  Work   November  19,  2013   28  
29. Thank  you!   November  19,  2013   29  
30. §  ADSP-­‐21489  SHARC  processor  from  Analog  Devices;   §  FT2232H  from  FTDI:   –  USB  2.0  High-­‐Speed  protocol.   §  XY  table  mo0on  control.   Processing  Core   November  19,  2013   30   Foto  de  qualquer  coisa??  
31. Amplifica1on  Chain   November  19,  2013   31   PGA DAC AD5621 Differential Probe Response Probe 20 dB 20 dB VCA821 AD8421 AD8421 VGAIN Amplified Probe Response
32. Eddy  Currents  Valida1on   November  19,  2013   32   −5 −4 −3 −2 −1 0 1 2 3 4 5 0 2 4 6 8 10 12 X [mm] Amplitude U/I [mΩ] Probe A at 1 MHz Probe B at 1 MHz [x5]
33. Driver  Cable  Inductance   Compensa1on   November  19,  2013   33   1k 10k 100k 1M 10M −40 −30 −20 −10 0 IO U T /VI N [dBS] Frequency [Hz] With Lsense Without Lsense
34. Spectogram   November  19,  2013   34