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Energy-Efficient 360-Degree Video Rendering on FPGA via Algorithm- Architecture Co-Design

HorizonLab
February 24, 2020

Energy-Efficient 360-Degree Video Rendering on FPGA via Algorithm- Architecture Co-Design

FPGA 2020 presentation. Presented by Qiuyue Sun.

HorizonLab

February 24, 2020
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  1. 360-Degree Video Delivery Pipeline Rendering Field of View (FOV) Consumes

    over 4 W power Exceeds TDP of typical mobile devices Original Frame
  2. Rendering 4 Current Rendering Algorithm Mapping Perspective Update Filtering Matrix

    Multiplication Cartesian Coordinates Linear Interpolation
  3. Challenges: Memory Accesses ▸ Irregular Access Pattern ▹Accesses are not

    sequential ▹Severely hurts the efficiency of hardware acceleration
  4. Challenges: Memory Accesses ▸ Irregular Access Pattern ▹Accesses are not

    sequential ▹Severely hurts the efficiency of hardware acceleration ▸ Large Footprint
  5. Challenges: Memory Accesses ▸ Irregular Access Pattern ▹Accesses are not

    sequential ▹Severely hurts the efficiency of hardware acceleration ▸ Large Footprint ▹1080P is ~5.9 MB and 4K is ~23.7 MB
  6. Challenges: Memory Accesses ▸ Irregular Access Pattern ▹Accesses are not

    sequential ▹Severely hurts the efficiency of hardware acceleration ▸ Large Footprint ▹1080P is ~5.9 MB and 4K is ~23.7 MB ▹Cannot be fully captured by a typical on-chip memory
  7. Our Design ▸ Enforce a streaming data access ▸ Reduce

    unnecessary computations (x’, y’) (x, y)
  8. Our Design ▸ Enforce a streaming data access ▸ Reduce

    unnecessary computations ▹Perform boundary checking
  9. Our Design ▸ Enforce a streaming data access ▸ Reduce

    unnecessary computations ▹Perform boundary checking ▸ Fully pipeline pixel rendering
  10. Setup and Evaluation 8 ▸ Xilinx Zynq UltraScale+ MPSoC ZCU104

    ▸ Pascal GPU on the Nvidia Jetson TX2
  11. Setup and Evaluation 8 ▸ Xilinx Zynq UltraScale+ MPSoC ZCU104

    ▸ Pascal GPU on the Nvidia Jetson TX2 ▸ Real User Trace Evaluation
  12. Setup and Evaluation 8 ▸ Xilinx Zynq UltraScale+ MPSoC ZCU104

    ▸ Pascal GPU on the Nvidia Jetson TX2 ▸ Real User Trace Evaluation ▸ Baseline: Original algorithm implemented on GPU and FPGA
  13. Setup and Evaluation 8 Energy Savings(%) 0 20 40 60

    RC Elephant NYC Rhino Paris Venice Saving over FPGA Savings over GPU ▸ Xilinx Zynq UltraScale+ MPSoC ZCU104 ▸ Pascal GPU on the Nvidia Jetson TX2 ▸ Real User Trace Evaluation ▸ Baseline: Original algorithm implemented on GPU and FPGA
  14. Setup and Evaluation 8 Energy Savings(%) 0 20 40 60

    RC Elephant NYC Rhino Paris Venice Saving over FPGA Savings over GPU ▸ Xilinx Zynq UltraScale+ MPSoC ZCU104 ▸ Pascal GPU on the Nvidia Jetson TX2 ▸ Real User Trace Evaluation ▸ Baseline: Original algorithm implemented on GPU and FPGA
  15. Setup and Evaluation 8 Energy Savings(%) 0 20 40 60

    RC Elephant NYC Rhino Paris Venice Saving over FPGA Savings over GPU ▸ Xilinx Zynq UltraScale+ MPSoC ZCU104 ▸ Pascal GPU on the Nvidia Jetson TX2 ▸ Real User Trace Evaluation ▸ Baseline: Original algorithm implemented on GPU and FPGA
  16. Conclusion 9 ▸ 360-degree video rendering consumes excessive power ▸

    Virtual reality popularity is growing rapidly
  17. Conclusion 9 ▸ 360-degree video rendering consumes excessive power ▸

    Our co-design achieves on average 26.4% and 40.0% energy savings over baselines ▸ Virtual reality popularity is growing rapidly