ExpectedIT - IT Press Tour #69 September 2026

Transcript

1. ExpectedIT · GERMAN DEEP TECH · Leveraging AI server infrastructure The next efficiency wave in AI datacenters ExpectedIT · Confidential
2. I. New management structure New management board supported by Klaus and Alex CEO Klas Moreau 2 ExpectedIT · Confidential CPO & Co-Founder CTO & Co-Founder Dr. Burkhard Steinmacher-Burow Àrni Ingimundarson Co-Founder Co-Founder Klaus Entenmann Alex Schwarz CFO Albert Weber
3. The team has built this before Experienced founder and management team CE O CP O & Co-fou n d er CT O & Co-fou n d er CF O Klas Moreau Dr. Burkhard SteinmacherBurow Àrni Ingimundarson Albert Weber 25 years of leadership in global deep tech companies Experienced CEO of VC backed semiconductor startups § § § § § 21 years IBM Senior Staff HW architect of datacenter supercomputers (Blue Gene) 100 patents on new HW&SW § § 6 years in the IBM POWER CPU design team 11 years chip development at Texas Instruments § § 20+ years of tech companies. VC backed, IPO, and exit Deep expertise in financial governance and scaling 16 engineers (doubling post-series A) + leadership Critical competencies in-house, Important partners identified and contracted 3 ExpectedIT · Confidential
4. I. The CPU is the new bottleneck There is a clear transition from GPU bottleneck to CPU bottleneck ERA 1 ERA 2 — NOW ERA 3 — FORMING Chat AI Agentic AI Inference-time learning Single queries NVLink makes the rack the GPU Token-factory economics Persistent 24/7 Tool calls, API, browsers CPU orchestrates everything 10x more CPU compute Bottleneck moves from GPUs to CPUs Models learn on the fly Parallel actor pools TB-scale replay buffers Memory and CPU bound $30B+ seed capital committed. These AI eras need scalable system architectures. Each successive wave needs more host HW (CPU, memory, network, storage). LPool advances CPU-based scale-up and scale-out for AI. 4 ExpectedIT · Confidential
5. I. The CPU is the new bottleneck AI performance is constrained by system architecture – not compute power. HOST BOTTLENECKS CPU ◼ stranded Memory ◼ stranded Storage ◼ stranded Stranded CPU cores => Shared resource The effective CPU capacity of the rack is not the sum of all cores. It is the capacity of the most constrained node at any given moment. Stranded memory => Shared resource Microsoft Research has documented memory stranding rates of 30–40% in production virtualised environments. Stranded storage throughput => Shared resource Network ◼ stranded NVMe drives attached to an idle node have throughput capacity sitting unused while a storage-bound workload on another node queues. Stranded network bandwidth => Shared resource A standard rack reaches ~2,048 CPUs in tier-1. LPool pools all rack NICs into one domain — multiplying tier-1 CPU reach by up to 9x. GPU availability matters less than utilization, memory paths, and I/O efficiency. Up to 50% more tokens from the same hardware — from hardware already paid for 5 ExpectedIT · Confidential
6. I. The CPU is the new bottleneck The market has already moved – Four sources from four angles AMD / Lisa Su Nvidia / Jensen Huang UBS Research Morgan Stanley Q1 2026 earnings May 2026 May 2026 April 2026 $120B 10x $170B 50–90% Server CPU TAM by 2030 more compute: agentic vs gen AI Server CPU TAM by 2030 of agentic workload latency is CPU-side Up 100% in one quarter — based on actual orders booked. "CPUs are becoming the bottleneck." Nvidia building CPU-only racks. 70–80% of compute burden shifts to CPU. 5× growth in 5 years. $32–60B incremental CPU TAM from agentic AI alone. "These are not projections. They are observations by people with direct visibility into the largest infrastructure orders in the world." 6 ExpectedIT · Confidential
7. II. LPool is the answer The host-side equivalent of what NVLink did for GPUs SOLVED 2022 THE OPEN PROBLEM NVLink LPool made the rack the GPU. • Erases boundaries between GPUs • Rack = one unified accelerator ≈ makes the rack the CPU. • Erases boundaries between CPUs • Rack = one coherent host machine Same architectural insight. Opposite side of the same rack. ExpectedIT is the company behind the LPool rack architecture. LPool is the coherent rack architecture that makes the host side of AI infrastructure work the way the GPU side already does. 7 ExpectedIT · Confidential
8. II. LPool is the answer One NUMA hop away – every socket count wins The rack is the configurable unit. ENTERPRISE & HPC • Build the servers that your workload needs, 8 sockets and beyond, all in one NUMA-connected pool HYPERSCALERS • Choose a server building block, then scale and configure capacity across the rack Either way, every CPU reaches the full rack’s memory, storage, and accelerators — one NUMA hop away. 8 ExpectedIT · Confidential
9. II. LPool is the answer AMD stops at 2. Intel stops at 8. LPool has no ceiling. SOA LPool 96S 48S 64S Sockets (log scale) 32S 16S 8S 4S 2S 1S HARD CEILING — no path beyond 8S Efficiency penalty AMD stops here 2S AMD Intel Gen 1 Gen 2 Gen 3 2 sockets max 8 sockets max 10 sockets 48 sockets 96 sockets 1S or 2S only 4S or 8S possible 2027 tapeout PCIe Gen 6 PCIe Gen 7 2x capacity = 4x cost DIMM and socket premium compounds fast 9 10S 8S ExpectedIT · Confidential Cheaper sockets, more of them. Smaller DIMMs × more sockets = better bandwidth per core at lower total cost Vendor-neutral. Intel, AMD, ARM. One open standard.
10. II. LPool is the answer Our LPool chip technology Our mission: AI with better costs & performance in Datacenters. Our target users: AI runs on GPU hardware, with host support (CPU, memory, network, storage). Our technology: Our LPool® chips unbottleneck the host support, for AI with better sustainability, costs nn PCIe tu ”The Pool chip dissolves the boundary between server nodes — making all their CPU cores, memory, and NICs equally accessible to every GPU in the rack." 10 ExpectedIT · Confidential el area Memory area
11. II. LPool is the answer A TECHNOLOGY TIPPING POINT UNLOCKS THE PROPOSED LPOOL 8S SERVERS 1-CPU server 11 ExpectedIT · Confidential CPU mem & devices | I/O CPU mem & devices I/O I/O mem & devices CPU x20 mem & devices mem & devices mem & devices mem & devices mem & devices mem & devices mem & devices mem & devices CPU CPU CPU CPU CPU CPU CPU CPU x64 LPoolTM may minimally-modify Arm or … protocol 4 x4 – LPool chip LPool chip LPool chip I/O Low-cost full-bandwidth server fabrics: I/O I/O Status quo 4+ CPU server Higher-cost: • A failed CPU wastes 3 other CPUs’ links. So, add costly redundancies I/O mem & devices I/O mem & devices Coherence uses broadcast-snoop, which bottlenecks bandwidth. I/O CPU x20 – I/O CPU CPU Most workload situations get only 1/3 of this fabric bandwidth: • Each CPU dedicates a link to each other CPU I/O I/O CPU I/O mem & devices I/O mem & devices I/O Lower-BW server fabrics: (Before tipping point) LPool chip 8-CPU LPool server. 2-CPU server (CPU may have minimally modified I/O. Scales to 32 CPUs with 16 pool chips) Today’s DC workhorse A HW tipping point enables our new LPool servers.
12. III. AI MARKET NEED & PRODUCT OPPORTUNITY AI INFERENCE EXAMPLE: AI NEEDS LARGE & FAST KV CACHE TO AVOID RE-COMPUTE ON GPUS 1X → Scale up the head node for more AI throughput → KV Cache: Status quo Distribute over many small head nodes 7X KV Cache: Opportunity Use 1 or few large head nodes or similar Same GPUs. Same Memory capacity. Same CPUs. Add CXL chips, to do more DMA & less RDMA (NICs & Network). ExpectedIT · Confidential Alibaba, “Beluga: A CXL-Based Memory Architecture for Scalable and Efficient LLM KVCache Management”, https://arxiv.org/abs/2511.20172
13. III. AI MARKET NEED & PRODUCT OPPORTUNITY AI INFERENCE EXAMPLE: AI NEEDS LARGE & FAST KV CACHE TO AVOID RE-COMPUTE ON GPUS 1X → Scale up the head node for more AI throughput → 7X KV Cache: Opportunity Use 1 or few large head nodes or similar KV Cache: Status quo Distribute over many small head nodes LPool chips Same GPUs. Same Memory. Same/similar CPUs. 1 4-CPU server 2 8-GPU boxes Add Lpool chips, for 1 large fast KV Cache. ExpectedIT · Confidential A modification of: “Beluga: A CXL-Based Memory Architecture for Scalable and Efficient LLM KVCache Management”, https://arxiv.org/abs/2511.20172
14. III. AI MARKET NEED & PRODUCT OPPORTUNITY AI INFERENCE EXAMPLE: AI NEEDS LARGE & FAST KV CACHE TO AVOID RE-COMPUTE ON GPUS 1X → Scale up the head node for more AI throughput → KV Cache: Opportunity Use 1 or few large head nodes or similar KV Cache: Status quo Distribute over many small head nodes Status quo AI rack of GPU servers: • 8 separate head nodes: • Each head node has 2 CPUs, for a domain of 8 GPUs. head node 0 ––– ––– head node 1 ––– ––– ––– head node 2 ––– ––– head node 3 ––– ––– head node 4 ––– ––– ––– head node 5 ––– ––– head node 6 ––– ––– head node 7 ––– ExpectedIT · Confidential 7X ––– AI rack: Status quo is similar to our proposal head node LPool Proposal AI rack of GPU servers: • 1 shared head node (or partitions), with LPool chips connecting the CPUs
15. IV. The market is large and open AI IS GROWING, AS ARE OUR LPOOL OPPORTUNITIES A. General-purpose servers B. Head node in GPU server Scale-up & -out efficiencies: • Workloads up to 10x faster 2x lower-cost Our competitors 15 Today’s focus 32-CPU LPool server + Expansion options ( e.g. 64+ AI PCIe cards) Our proposal (Examples) Our advantage Adjacent opportunities ExpectedIT · Confidential 1- or 2-CPU Server • Today’s workhorse • Expansion options Adjacent opportunities C. AI host server LPool minimally modifies head node: • 8-GPU server • 72-GPU rack • Various vendors 8S-2048 LPool cluster: • 8 CPUs per server • 2048 CPUs in 1st tier of network Scale-up & -out efficiencies of unified host HW. E.g. 16384 GPUs in 1st tier of datacenter network Scale-up & -out efficiencies for global AI Serving & Coordination. Original non-LPool GPU servers: • Nvidia NVL8 or NVL72 rack. • AMD 8-GPU or Helios rack. • AWS, Google, … 1- or 2-CPU Server • 1S-256 or 2S-512
16. IV. The market is large and open OUR NEW 8+ CPU SERVERS: A NEW POTENTIAL ~$10B SEGMENT FOR CPUS & LPOOL CHIPS CPU TAM ($B) for Datacenters Worldwide 200 180 8+ CPU AI host servers: ← A potential ~$10B segment* for CPUs & LPool chips. 160 140 8+ CPU AI head nodes: ← A potential ~$10B segment* for CPUs & LPool chips. 120 100 80 * Derived estimates; to validate with Intel. 60 40 ← Adjacent LPool opportunities 20 0 2025 2027 UBS est. Traditional servers AI CPU servers (agent+host) AI Head Node ExpectedIT · Confidential AI agent servers 1- or 2-CPU 2030 UBS est. AI head node 1- or 2-CPU AI host servers 1- or 2-CPU 2030 ExpectedIT est. AI head node 8+ CPU LPool AI host servers 8+ CPU LPool UBS forecast via https://www.bitget.com/news/detail/12560605398889
17. IV. The market is large and open From a large market to a focused opportunity. TAM Server CPU market by 2030 $150B Midpoint of AMD ($120B) and UBS ($170B). Up from ~$30B today — a fivefold increase in five years driven by agentic AI. SAM Lpool compatible CPUs and Lpool chips segment $30B Net-new CPU demand created specifically by agentic AI. Morgan Stanley independently estimates $32–60B incremental CPU TAM. SOM IP licensing & royalties + fabless manufacturing $200 + 200M IP licensing fees + per-chip royalties for host and fabless manufacturing of the Lpool chip. S ERI ES A €25M (incl. €10M EIC equity) · Milestone: tapeout 2027 · production deployment 2028 17 ExpectedIT · Confidential
18. V. The model scales A capital-efficient base case with compounding upside. LAYER 1 LAYER 2 LAYER 3 IP Licensing Fabless Chip Manufacturing Platform Standard Royalty per CPU and Lpool SKU* shipped. Own the Pool chip. Sell direct to server OEMs. LPool becomes the coherent rack standard. CAPITAL CAPITAL CAPITAL €25M Series A €60M Series B No additional dilution REVENUE REVENUE REVENUE ~€200M by 2032 ~€400M combined L1+L2 by 2032 Certification + per-rack software + exit optionality Low capital. High margin. Higher per-unit revenue. Direct customer relationships. Exceptional outcome scenario. "Series A funds a standalone profitable business. Series B doubles it. The platform layer is the scenario that makes this an exceptional outcome." 18 ExpectedIT · Confidential * = SKU – Stock Keeping Unit
19. V. The model scales Financial performance forecast: strong revenue and EBIT growth. Revenue (€M) EBIT (€M) · Gross margin → ~75% 450 350 398 400 301 300 350 250 300 200 250 204 200 150 100 101 100 50 149 150 74 50 32 5 3 0 22 0 2028 2029 2030 2031 2032 2028 2029 2030 2031 2032 Revenue model: IP licensing (Layer 1) + fabless chip (Layer 2, from Series B). Layer 1 alone delivers ~€200M by 2032 at >70% gross margin. S E R I E S A : €25M including €10M EIC equity · Tapeout ready 2027 · First CPU vendor license 2027 · Production deployment 2028 19 ExpectedIT · Confidential
20. IV. The market is large and open Four buyer types, one licensing entry point – CPU vendors first Hyperscalers AI Cloud Providers AWS · Azure · Google · Meta CoreWeave · Lambda · Crusoe · Together AI § Reduce total cost up to 50% more tokens § Maximize GPU utilization § Scale clusters more efficiently · Gain competitive edge in AI infrastructure · Higher performance per rack · Faster deployment & scaling GPU Server OEMs ExpectedIT LPool CPU Vendors BEACHHEAD NVIDIA · Dell · HPE · Supermicro · Bull Intel · AMD · ARM · Qualcomm · SiPearl · Differentiate next-gen AI systems · Enable higher-performance server designs · Improve system-level efficiency · Reclaim relevance in AI infrastructure · Increase CPU utilization in AI workloads · Strengthen ecosystem positioning 20 ExpectedIT · Confidential
21. VI. The team has built this before Progress since spring 2026. PROOF POINTS WHAT’S NEXT Verified, in progress, and what’s next What capital unlocks, and who has to say yes DONE Memory directory chip logic Complete; passed initial TSMC N6 backend process PHASE 0 — Now → Series A close DONE Cross-CPU PCIe device sharing 1st working FPGA-based demo of LPool-style sharing across CPUs, including SW stack DONE Core architecture thesis Independently confirmed by engineering teams at Microsoft and Meta. "This LPool technology is actually something truly new to bring into how we build servers, and a promising one” (Microsoft VP) DONE Intel UPI endorsement Licensing agreement in place Demo results (Sept 2026), Intel’s backing, Core42 & SiPearl signed. Round opens Oct 2026, closes end of March 2027. PHASE 1 — Series-A close → Tapeout-ready (2027) Remaining silicon verification. First CPU vendor license. Backend team for chip implementation & test already secured. PHASE 2 — Tapeout ready→ Production (2028) Datacenter pilot moves to live production deployment. Series B raised for fabless volume manufacturing. IN PROGRESS AI-relevant workload demo LPool-enabled vs. non-LPool-enabled comparison — results by end of September 2026 NOT STARTED LPool chip verified against Intel CPU Next milestone, once Intel endorsement lands 21 ExpectedIT · Confidential Will be dynamically updated with the latest progress.
22. VI. The team has built this before Traction and validation. "This LPool technology is actually something truly new to bring into how we build servers, and a promising one” Microsoft VP – Offered to give verbal support for the technology to VC in DD process LETTER OF INTENT COMMERCIAL VALIDATION Demand from every layer of the customer stack We are discussing scope of technical demonstration with Microsoft Workloads • FractalBrain (SIGNED) — Frontier AI developer Design partner and early adopter for inference-time learning workloads. Validates demand from the post-LLM generation of AI that LPool is built for, from the researchers building it. We are in advanced discussions with a Tier-1 CPU vendor Infrastructure • Core42 (a G42 company) (SIGNED) — Sovereign AI cloud operator Early operator and reference for agentic AI at national scale, on a roadmap toward 32-socket dense racks. Validates demand at hyperscale, where the agentic thesis bites first. • 1984 ehf (SIGNED) — Cloud and hosting operator Pilot and reference deployment in its renewable-powered Icelandic datacenter. Validates the virtualisation and efficiency value proposition, and gives LPool a live operator testbed. Silicon • SiPearl (PENDING) — European CPU vendor Host-side coherence for the European rack-scale AI platform, with IP integration into a future CPU generation as the longer step. Validates the licensing path: the customer type that ships LPool in silicon. 22 ExpectedIT · Confidential EIC ACCELERATOR — TOP 4% EU-WIDE Grant: €2.5M Equity: €10M (Series-A co-investment) EUROCDP VENTURE DEVELOPMENT PROGRAMME SEED FUNDING RUNWAY €6.5M from Investors – Runway to Sept 2027 Will be dynamically updated with information about additional customer engagements.
23. VI. The team has built this before New Advisory Board to support management team Chairman Klaus Entenmann 23 ExpectedIT · Confidential Member Vinton G. Cerf Member Peter Vinnemeier Member Raj Singh Member US Hyperscaler Executive Member Brian Fyda
24. VI. The team has built this before Answering your questions. 1 Does the architecture actually work, or is it still a paper design? 2 Hyperscalers are reducing server variants — is there a real buyer? 4 What stops a larger player from building this themselves? 6 → Chip logic complete, past TSMC N6 backend. Working PCIe cross-CPU demo. Core thesis independently confirmed by Microsoft and Meta engineering — not just our own claims. 3 → Intel UPI endorsement in place. SiPearl LOI pending. First signed CPU vendor license targeted 2027. → That’s the point, not the problem. LPool connects various server building blocks like those already in the fleet. 5 → Core patents filed in EU and US, more in preparation. Moat is being first to lock in CPU vendor licensing. 24 ExpectedIT · Confidential Will any CPU vendor actually build this in? Can a 20-person team hit a 2027 tapeout? → Leadership built IBM Blue Gene and IBM POWER. Top 4% of 1,000+ EIC applicants. Backend team secured; headcount doubles post-close. Will they run out of cash before the round closes? → Runway to September 2027 — six months past the planned close. Round opens October 2026, closes end of March 2027.
25. VII. The case for investing now Investment case: owning the next scaling layer of AI infrastructure. 1 3 We solve a structural bottleneck in AI infrastructure. Up to 50% more tokens from the same hardware 2 Market growing fivefold to $120–170B by 2030. → CPU-side orchestration = 50–90% of agentic workload latency (Morgan Stanley, Apr 2026) → Four independent sources: AMD Q1'26, Nvidia May'26, UBS May'26, Morgan Stanley Apr'26. Scalable monetisation with strong margin potential. Team has built this before. IP-protected. EIC-validated. → Component sell and IP licensing. 4 → Top 4% of 1,000+ EIC applicants. IBM Blue Gene/Q. IBM POWER. 10 patents filed for LPool. "The rack is the CPU." 25 ExpectedIT · Confidential
26. VIII. The ask Where we are, and what we’re looking for. THE ROUND LET’S TALK Capital, structure, and where things stand Open to lead or follow, at check sizes that fit your fund. €25M Series A, including up to €10M EIC equity Opens October 2026 · targets close by end of March 2027 Natural next step, whichever fits: Lead identification underway. Consortium forming. → Technical deep-dive with Burkhard on the LPool architecture Milestones: tapeout-ready 2027 · first CPU vendor license 2027 · production deployment 2028 → Reference calls with Microsoft, FractalBrain and 1984 ehf → Data room access 26 ExpectedIT · Confidential Let’s find the shape that works for you.
27. "The rack is the CPU." Let's build the next layer. ExpectedIT GmbH www.expected-it.com CEO: Klas Moreau klas.moreau@expected-it.com ExpectedIT · Confidential