Introduction to VHDL

Introduction to VHDL. Elements of VHDL and abstraction levels of VHDL.

Transcript

1. Introduction to VHDL By Dr Madhuri Mulik ECE Dept. SITCOE, Yadrav Ichalkaranji
2. What is VHDL? •Definition & Acronym: VHDL stands for VHSIC Hardware Description Language, where VHSIC stands for Very High Speed Integrated Circuit. •Core Function: It is a hardware description language used to model and describe the behavior of physical integrated circuits or digital systems. •Key Attributes: It is a standard, portable, reusable, and vendor-independent language. •Levels of Abstraction: It can model digital systems across multiple levels of abstraction. •Target Applications: VHDL code is used to implement circuits on programmable hardware such as Complex Programmable Logic Devices (CPLDs) and Field Programmable Gate Arrays (FPGAs), or for the fabrication of Application-Specific Integrated Circuit (ASIC) chips.
3. What is Verilog? •Definition & Core Function: Verilog is a text-based Hardware Description Language (HDL) used to describe the structure and behavior of digital circuits. •Design & Simulation: It enables designers to model and simulate circuits in software before physically manufacturing them. •Standardization: It is an industry-standard language verified and maintained by the Institute of Electrical and Electronics Engineers (IEEE). •Concurrency: Supports concurrent modeling to accurately simulate simultaneous, parallel processes in hardware (similar to VHDL). •Levels of Abstraction: Supports multiple abstraction levels, allowing circuits to be described at varying degrees of detail. •Scalability: Designed to effectively manage large-scale projects, making it ideal for complex digital circuit design.
4. Comparison of VHDL and Verilog VHDL Verilog VHDL is based on Pascal or ADA language Verilog is based on C programming language VHDL is not case sensitive. Verilog is case sensitive. VHDL does not have compiler directives Verilog has compiler directives VHDL does not supports transistor level modelling Verilog supports transistor level modelling. VHDL support user defined data types. Verilog does not support user defined data types.
5. Features of VHDL • It supports hierarchy. It uses set of components and interconnects them, each component can also be modeled as a set interconnected sub components. • It supports both synchronous and asynchronous timing models. • It supports various digital modeling techniques like Finite State Machine (FSM), Algorithmic description and Boolean expressions. • It is not case sensitive. • The logical operation and timing behavior of a design can be stimulated. • It is not technology specific i.e. it can work with Xilinx, Lattice, Atmel series of CPLDs or FPGAs.
6. Elements of VHDL 1) Entity (Interface Definition) The fundamental building block of a VHDL design that declares the design name and defines its input and output interface. Syntax entity ENTITY_NAME is port (port list); end ENTITY_NAME;
7. Elements of VHDL 2) Architecture (Internal Logic & Behavior) Describes the internal implementation and behavioral relationship between the inputs and outputs of an entity. Every entity must have at least one associated architecture; a single entity can have multiple architectures. Syntax architecture ARCHITECTURE_NAME of ENTITY_NAME is -- Declarations (types, signals, constants, subprograms) begin -- Statements (functional relationship between inputs & outputs) end ARCHITECTURE_NAME;
8. Elements of VHDL 3) Configuration (Component Binding) • Maps and binds a specific component instance to an entityarchitecture pair. • Crucial during structural design instantiation when an entity has multiple architecture implementations. • Allows selection of target implementations without altering original source code.
9. Elements of VHDL 4) Package (Reusability & Organization) • Definition: A container for commonly used data types, constants, and subprograms. • Key Benefits: • Reusability: Sharable across multiple entities and projects. • Organization: Simplifies code management by centralizing global definitions. • Modularity: Promotes structured, maintainable hardware design practices.
10. Elements of VHDL 5) Library (Storage Repository) • Definition: A designated design storage location for VHDL programs. • Stored Elements: Holds compiled design units, including: • Entities • Architectures • Packages -- Library Clause: Declare the library name library IEEE; -- Use Clause: Import all definitions from std_logic_1164 package use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_arith.ALL; use IEEE.STD_LOGIC_unsigned.ALL;
11. VHDL Modeling Styles • The different modeling types provided by VHDL are : Overview of VHDL Modeling Styles • Three Primary Abstraction Styles: VHDL provides three distinct approaches to model digital hardware based on design complexity and structural abstraction: • Dataflow Modeling (Concurrent / Boolean level) • Behavioral Modeling (Algorithmic / Sequential level) • Structural Modeling (Schematic / Component level) • Design Flexibility: Engineers can mix and match these modeling styles within a single project depending on the component requirements.
12. Dataflow Modeling Style • Core Concept: Describes how data flows through the circuit using Boolean equations and concurrent signal assignment statements. • Order Independence: Statement position in the architecture body does not matter; all assignment statements execute simultaneously in parallel. • Primary Focus: Concentrates on signal relationships and data processing pathways rather than physical component boundaries. library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Mux2to1 is Port ( A : in STD_LOGIC; B : in STD_LOGIC; Sel : in STD_LOGIC; Y : out STD_LOGIC ); end Mux2to1;
13. architecture Dataflow_Arch of Mux2to1 is begin -- Boolean logic expression executed concurrently Y <= (A and (not Sel)) or (B and Sel); -- Alternative equivalent syntax using conditional signal assignment: -- Y <= A when Sel = '0' else B; end Dataflow_Arch;
14. Behavioral Modeling Style Uses a procedural, sequential programming approach (similar to software) within VHDL process blocks. •Control Flow Statements: Employs conditional control flow mechanisms like if-then-else and case statements to react to input changes. •Primary Focus: Defines system behavior and high-level logic under varying conditions without requiring structural details. architecture Behavioral_Arch of Mux2to1 is begin -- Process executes sequentially when any signal in the sensitivity list changes process (A, B, Sel) begin if Sel = '0' then Y <= A; else Y <= B; end if; end process; end Behavioral_Arch;
15. Structural Modeling Style • Core Concept: Connects pre-defined, pre-verified hardware components (entities) together like a physical circuit board schematic. • Instantiations & Mapping: Instantiates component entities with unique names and wires their port connections (port mapping). • Primary Focus: Prioritizes component hierarchy and interconnection over internal algorithmic operations.
16. architecture Structural_Arch of Mux2to1 is -- Component Declarations component NOT1 Port ( In1 : in STD_LOGIC; Out1 : out STD_LOGIC ); end component; component AND2 Port ( In1, In2 : in STD_LOGIC; Out1 : out STD_LOGIC ); end component; component OR2 Port ( In1, In2 : in STD_LOGIC; Out1 : out STD_LOGIC ); end component; -- Internal signals (wires) signal Sel_Not : STD_LOGIC; signal Term1 : STD_LOGIC; signal Term2 : STD_LOGIC; begin -- Component Instantiations and Port Mapping U0: NOT1 port map ( In1 => Sel, Out1 => Sel_Not ); U1: AND2 port map ( In1 => A, In2 => Sel_Not, Out1 => Term1 ); U2: AND2 port map ( In1 => B, In2 => Sel, Out1 => Term2 ); U3: OR2 port map ( In1 => Term1, In2 => Term2, Out1 => Y ); end Structural_Arch;
17. Thank you