This presentation is among the Top 27 Best Papers/Practice/Tutorials selected, out of 460+ submissions received, to be presented @STC 2012.
In today’s age most of the automobiles, airplanes, power plants, etc. are controlled by computer systems interacting in real time environments. Failure of real time systems endangers the human life. A common cause of failure is timing violations; i.e., the deadlines are missed. It is one of the performances of the software. The best way to predict the execution timing performance is, by performing the Worst Case Execution Timing Analysis (WCET) that helps to address the failures due to overshooting of allocated time. The goal of the Worst Case Execution Timing exercise is to assess the timing of the embedded system design thereby increasing the confidence of robustness/stability of the system. It is a key component when designing and verifying real-time systems, especially when used to control safety-critical systems.
The approach used for Worst Case Execution Timing analysis is analyzing the call tree and executing the respective paths.
About the Author
K S Sreetha is a Software Engineer with Eaton Technologies Pvt. Ltd. She has around 6.5 years of software experience in Independent Verification and Validation activities in the Avionics domain for Embedded C Projects. Her core skills include System Level Testing , Unit level Testing , Regression Testing , Stack and Timing Analysis for the embedded products and Compliance with the safety guidelines for aerospace(DO-178B). She also has hands on experience in Hardware in loop testing.
Prior to joining Eaton, Sreetha was with HCL Technologies and before that a Research Fellow at Aeronautical Development Agency. She has worked in prestigious projects like Boeing Dreamliner 787 and Tejas (LCA).
Sreetha graduated as a topper from Bharathiar University receiving her undergraduate degree in Electrical and Electronics Engineering. She also topped her batch in the MS Embedded Systems program from BITS Pilani