Christophe Moy - Software Radio Research for Reconfigurable Wireless Physical Layers

Fef83ca87fd2a7994d087631868acf8f?s=47 SCEE Team
October 07, 2004

Christophe Moy - Software Radio Research for Reconfigurable Wireless Physical Layers

Fef83ca87fd2a7994d087631868acf8f?s=128

SCEE Team

October 07, 2004
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  1. Software Radio Research for Reconfigurable Wireless Physical Layers Jeudi 7

    octobre 2004 Supélec - Rennes Christophe Moy Mitsubishi Electric ITE Telecommunication Laboratory ITE research on SDR 1 outline • software radio in ITE • hardware platforms for experiments • digital radio on generic hardware • reconfiguration • design methodology perspectives • collaborations • conclusions
  2. ITE research on SDR 2 software radio research in ITE

    • SWR research in ITE since early 1999 • research activity • 3 engineers + 1 PhD student • ~15 papers in international conference • invitation to IEEE RAWCON'03 SDR Workshop in Boston (Aug. 2003) invitation to ANWIRE'2003 in Mykonos, Greece (Oct. 2003) • representation of Mitsubishi Electric at SDR Forum & WWRF • Collaborations internally to Mitsubishi Electric – 3 years with Mobile BU in Rennes: MMCE (Trium R&D) – 3 years with Semiconductor BU (Renesas now) • RNRT A3S - Adéquation Architecture / Application Système • IST E²R - End-to-End Reconfigurability SWR in ITE HW platforms digital radio reconfiguration design methodology collaborations conclusions ITE research on SDR 3 what is software radio? • digital conversion as close as possible of the antenna • specialization of the system in the digital domain, if possible in SW • in order to benefit from the digital domain – design techniques • computer aided design tools... – technologies • low power consumption, • small size... – digital signal processing advantages for telecommunications • robustness, protection capabilities, • capacity... – reconfigurability • processors • reconfigurable HW • parameterizable ASICs SWR in ITE HW platforms digital radio reconfiguration design methodology collaborations conclusions real new feature that implies new radio paradigm
  3. ITE research on SDR 4 software radio in the large

    scale • many research areas around software radio (examples) – design issues • HW components design & technology: processors architecture, FPGA, ADC/DAC, power amplifiers, filters, antennas, MEMS, communication media, SoC, NoC... • SW design: compilers, multi-processing, high-level HW/SW co-design & verification, SW frameworks for reconfiguration, distributed management... – signal processing • digital radio, multi-standard, algorithm parameterization, environment characterization, MIMO... – network management • inter-standard hand-over, reconfiguration orders management, reconfiguration state management... – regulatory aspects • type of approval, spectrum management policy, SDR standard… – security • encryption, protocols… – cognitive radio – ... SWR in ITE HW platforms digital radio reconfiguration design methodology collaborations conclusions ITE research on SDR 5 manufacturer's interest in software radio • Mitsubishi Electric – 2G infrastructure (PDC, PHS in Japan) – 2G mobile phones (PDC & PHS in Japan, GSM/GPRS in Europe and USA) – 3G mobile phones (FOMA in Japan) • SDR advantages from the infrastructure point of view – system adaptability to specific context – system migration from one generation to the other • SDR advantages from the mobile manufacturer point of view – time to market - shorter development time – same design for several market – bug fixing, maintenance – multi-mode, multi-standard SWR in ITE HW platforms digital radio reconfiguration design methodology collaborations conclusions
  4. ITE research on SDR 6 areas of interest • HW

    architecture – reconfigurability (potential) • processors (SW), reconfigurable HW, parametrizable ASICs – computing power (potential) • multi-processing (SoC or distributed), heterogeneity • communication media • digital radio processing – digital signal processing – SW and reconfigurable HW signal processing IPs • SW architecture for reconfiguration – component-based approach – OTAR • design methodology for heterogeneous platforms or SoC – concentrating on physical layer SWR in ITE HW platforms digital radio reconfiguration design methodology collaborations conclusions processing boards and circuits architecture platform/application abstraction reconfiguration management IP design methodology ITE research on SDR 7 • software radio in ITE • hardware platforms for experiments • digital radio on generic hardware • reconfiguration • design methodology perspectives • collaborations • conclusions
  5. ITE research on SDR 8 requirements for SWR keywords •

    genericity (many different applications are possible) • heterogeneity (processors, digital ASICs, analog ASICs, GPP, possible FPGA...) • modularity (many daughter boards are available) • scalability (other boards may be added in the same rack) • reconfigurability (thanks to parametrizable ASICs, processors and FPGAs) • portability (C language whatever processor, VHDL for FPGAs) • digital or software IF (DDC and DUC that are bypassable) • ease of use during development stage (multi-host remote access) • SW co-design tools (automatic code generation) SWR in ITE HW platforms digital radio reconfiguration design methodology collaborations conclusions ITE research on SDR 9 COTS platforms all the elements that will be present in future SWR systems • heterogeneous computing – programmable (DSP, GPP) – reconfigurable HW (FPGA) – parameterizable ASIC (DDC, DUC, ADC, DAC) – analog ASIC (PA, filters) • heterogeneous communications – FIFO, bus, TCP, shared memory • digital IF – through parameterizable ASIC (DDC, DUC) – directly from DSP or FPGA (bypass ASIC) SWR in ITE HW platforms digital radio reconfiguration design methodology collaborations conclusions processing mother board TX: D/A & DUC daughter board RX: A/D & DDC daughter board
  6. ITE research on SDR 10 DSP - C6x processors •

    TMS320C6201 : Virgule fixe – 1600 MIPS @ 200 MHz • Architecture VLIW – 8 instructions en parallèle – 2 Multiplieurs – 6 ALUS – software pipeline • Mémoire & périphériques – RAM interne 128 kB (64kB prog./64kB data) – Interface EMIF (External Memory Interface) – 4 Contrôleurs DMA • TMS320C6203 – 2400 MIPS à 300 MHz – RAM: 512 kB /364 kB • TMS320C6416 – 4800 MIPS à 600 MHz SWR in ITE HW platforms digital radio reconfiguration design methodology collaborations conclusions high-performance compiler ITE research on SDR 11 FPGA - Virtex-II • XC2V3000 – 3 million gates – 14336 slices – 28672 FlipFlops & LUT – 1.728 Mbits embedded RAM – 448 kbits distributed mem – 96 multipliers (18x18 bits) – 720 I/O – Active interconnect routing matrix • XCV8000 – 3.024 Mbits emb. RAM – 1456 kbits distributed mem – 168 multipliers SWR in ITE HW platforms digital radio reconfiguration design methodology collaborations conclusions
  7. ITE research on SDR 12 experimentation platforms PENTEK • multi-fixed

    point DSP board – 4 TI C6203 DSPs @300 MHz – high speed bi-FIFO comm links – host - target ethernet link (100 Mb/s) • 2 channel wideband Tx module – upconverter (DUC), D/A converter – upconverter is bypassable – programmable parameters • 2 channel wideband Rx module – A/D converter, downconverter (DDC) – downconverter is bypassable – programmable parameters • 2 x XC2V3000 Xilinx generic hardware platforms for experimentation and demos SWR in ITE HW platforms digital radio reconfiguration design methodology collaborations conclusions LSP LYRtech • floating point DSP board – C6701 DSP @166 MHz • 2 channel wideband Tx/Rx module • XC2V1000 Xilinx • Simulink design to heterogeneous HW direct implementation Sundance (DSP+FPGA) • in cooperation with IETR/INSA – INSA: Communication Propagation Radar – INSA: Image and Teledetection ITE research on SDR 13 • software radio in ITE • hardware platforms for experiments • digital radio on generic hardware • reconfiguration • design methodology perspectives • collaborations • conclusions
  8. ITE research on SDR 14 case study I: timings DSPs

    DSPs: 4 x TI C6201 : 4 x TI C6201 Tx Tx: DUC + D/A : DUC + D/A Rx: A/D + Rx: A/D + DDC DDC UMTS FDD GSM/DCS EDGE BlueTooth Symbol rate (kbds) 3840 270.833 270.833 1000 T (µs) 0.2604 µs 3.69 µs 3.69 µs 1 µs multiple access DS-CDMA FH-TDMA TDMA FH-CDMA time slot 667 µs 576.9 µs 576.9 µs 625 µs 1600 hops/s modulation QPSK (DL) BPSK (UL) GMSK h: 0.5 3π/8 Offset 8-PSK GFSK h: 0.28 - 0.35 pulse shaping Root Raised Cosine (RRC) roll off: 0.22 Gaussian (premod) BT: 0.3 Gaussian Gaussian BT: 0.5 data rate (kbits/s) 144-2000 9.6-13 < 384 1000 Tx Modulator Rx Demodulator Modem Req. Perf. ksym/s C6201 200MHz C64x 1GHz C6201 200MHz C64x 1GHz UMTS-HD 3840 960.8 4804 879.1 4395.5 UMTS-FS 3840 1434.2 7172 1435.3 7176.5 GSM 270.83 444.6 2223 753.56 3767.8 EDGE 270.83 1036 5180 506.73 2533.65 Bluetooth 1000 444.6 2223 825.49 4127.45 SWR in ITE HW platforms digital radio reconfiguration design methodology collaborations conclusions ITE research on SDR 15 This experiment permitted to gain useful insight on: digital signal processing techniques for all digital modem implementations e.g. undersampling, filter banks, synchronization digital-IF, soft-IF transceiver designs both multiprocessor and single processor configurations This experiment permitted to gain useful insight on: digital signal processing techniques for all digital modem implementations e.g. undersampling, filter banks, synchronization digital-IF, soft-IF transceiver designs both multiprocessor and single processor configurations case study I: timings DSPs DSPs: 4 x TI C6201 : 4 x TI C6201 Tx Tx: DUC + D/A : DUC + D/A Rx: A/D + Rx: A/D + DDC DDC UMTS FDD GSM/DCS EDGE BlueTooth Symbol rate (kbds) 3840 270.833 270.833 1000 T (µs) 0.2604 µs 3.69 µs 3.69 µs 1 µs multiple access DS-CDMA FH-TDMA TDMA FH-CDMA time slot 667 µs 576.9 µs 576.9 µs 625 µs 1600 hops/s modulation QPSK (DL) BPSK (UL) GMSK h: 0.5 3π/8 Offset 8-PSK GFSK h: 0.28 - 0.35 pulse shaping Root Raised Cosine (RRC) roll off: 0.22 Gaussian (premod) BT: 0.3 Gaussian Gaussian BT: 0.5 data rate (kbits/s) 144-2000 9.6-13 < 384 1000 Tx Modulator Rx Demodulator Modem Req. Perf. ksym/s C6201 200MHz C64x 1GHz C6201 200MHz C64x 1GHz UMTS-HD 3840 960.8 4804 879.1 4395.5 UMTS-FS 3840 1434.2 7172 1435.3 7176.5 GSM 270.83 444.6 2223 753.56 3767.8 EDGE 270.83 1036 5180 506.73 2533.65 Bluetooth 1000 444.6 2223 825.49 4127.45 SWR in ITE HW platforms digital radio reconfiguration design methodology collaborations conclusions Tx Modulator Rx Demodulator Modem Req. Perf. ksym/s C6201 200MHz C64x 1GHz C6201 200MHz C64x 1GHz UMTS-HD 3840 960 4804 879 4395 UMTS-FS 3840 1434 7172 1435 7176 GSM 270.83 444 2223 753 3767 EDGE 270.83 1036 5180 506 2533 Bluetooth 1000 444 2223 825 4127 targeted data rate for R/T OK @ 200 MHz for GSM & EDGE OK @ 1 GHz for all digital processing methods to decrease computational complexity
  9. ITE research on SDR 16 DSP Processor Digital ASIC modules

    fdac QPSK modulator Restitution Board DAC Bits Generation QPSK mapping Pulse Shaping (RRC Filter) N Upconvert real data 0, 1 I, Q IF fLO fdac fadc QPSK demodulator Acquisition Board ADC Sampling Time Recovery best sample position BER measurement Frame Synchronization sync pattern position N Phase Correction Decision Matched Filter (Polyphase Bank) Downconvert polyphase filter coeff. I, Q 0, 1 angle Compute Phase Offset IF fLO fadc real data Interpolating Filter: 8 Interpolating Filter: 8 DDS 2 MHz I Q sin cos Complex Mixer DDS 2 MHz Decimating Filter: 8 Decimating Filter: 8 I Q sin cos Complex Mixer UMTS-HD: mapping on DSPs and ASICs SWR in ITE HW platforms digital radio reconfiguration design methodology collaborations conclusions ITE research on SDR 17 DSP Processor Digital ASIC modules DSP Processor Digital ASIC modules fdac QPSK modulator Restitution Board DAC Bits Generation QPSK mapping Pulse Shaping (RRC Filter) N Upconvert real data 0, 1 I, Q IF fLO fdac fadc QPSK demodulator Acquisition Board ADC Sampling Time Recovery best sample position BER measurement Frame Synchronization sync pattern position N Phase Correction Decision Matched Filter (Polyphase Bank) Downconvert polyphase filter coeff. I, Q 0, 1 angle Compute Phase Offset IF fLO fadc real data UMTS-FS: full software mapping SWR in ITE HW platforms digital radio reconfiguration design methodology collaborations conclusions
  10. ITE research on SDR 18 fast digital frequency conversion SWR

    in ITE HW platforms digital radio reconfiguration design methodology collaborations conclusions with f0 = (n ± ¼ ) fs cos(kTs ) = 1 0 -1 0 sin(kTs ) = 0 1 0 -1 Up Up- -conversion conversion Down Down- -conversion conversion 1 0 -1 0 sin cos Complex Mixer sin cos Complex Mixer 0 1 0 -1 Calculate only Calculate only 1 over 2 1 over 2 output output samples samples Use only Use only 1 over 2 1 over 2 input input samples samples ITE research on SDR 19 "IF-undersampling" Tx SWR in ITE HW platforms digital radio reconfiguration design methodology collaborations conclusions I Q C6201 12-bit D/A fS Periodic spectrum due to sampling 2.fS BPF d f e fDAC Interpol. Filter: 8 Interpol. Filter: 8 2.fDAC ¼ fDAC ½ fDAC Sampling frequency fDAC DDS sin cos Complex Mixer 2.fDAC fS fDAC IF spectrum fDAC 2.fDAC (1+1/4).f DAC = IF c c d e f A "high" frequency signal is generated with a low computing rate BB signal
  11. ITE research on SDR 20 IF-undersampling Rx SWR in ITE

    HW platforms digital radio reconfiguration design methodology collaborations conclusions BPF ( ) f X + RF or IF spectrum IF IF ( ) s f f X 3 + + ( ) s f f X 2 + + ( ) s f f X + + ( ) s f f X − + ( ) s f f X 2 − + ( ) s f f X 3 − + ) L fADC 2 fADC ( ) ( ) ∑ ∞ −∞ = − = n s s s nf f X T f X 1 Undersampling (2 + ¼) fs = IF ¼fs ( ) (L s s T f X 1 = Undersampling low needs in processing power by reducing sample rate fS < 2 fmax fS >2 B fS = 4 IF /5 Signal that will be finally demodulated (low computing rate) Received signal Digitized signal ITE research on SDR 21 GSM SWR in ITE HW platforms digital radio reconfiguration design methodology collaborations conclusions DDS DAC sin cos Complex Mixer Decim Filter 8 Decim Filter 8 RF Out sin cos Complex Mixer ADC RF In Gaussian filter 4Ç NRZ Bits 4È Decision FSK BER DDS Inter Filter 8 Inter Filter 8 FSK h=0.5 Phase calculation (Cordic) Tx Maximal Performance : 1.7 Msamples/s (425 ksymbols/s) Rx Maximal Performance : 2.7 Msamples/s (675 ksymbols/s) f o = 2 MHz f bits = 250 kbits/s f symbols = 250 ksymbols/s over = 4 f samples = 1 Msamples/s f DAC = 8 MHz IF = 10 MHz f ADC = 8 MHz f o = 2 MHz GMSK
  12. ITE research on SDR 22 EDGE SWR in ITE HW

    platforms digital radio reconfiguration design methodology collaborations conclusions DDS DAC I Q sin cos Complex Mixer Decim Filter 8 Decim Filter 8 RF Out sin cos Complex Mixer ADC RF In Edge filter Edge Filter 8Ç 8Ç Mapping 8-PSK Bits Decision 8 PSK (Cordic) BER Zero forcing Filter Zero forcing Filter 8È 8È DDS Inter Filter 16 Inter Filter 16 Rotation 3 pi / 8 (8-PSK to 16-PSK) Rotation -3 pi / 8 (16-PSK to 8-PSK) Maximal Performance : 2.333 Msamples/s (291 ksymbols/s) f bits = 750 kbits/s f symbols = 250 ksymbols/s over = 8 f samples = 2 Msamples/s f DAC = 32 MHz IF=2 MHz f ADC = 8 MHz f o = 2 MHz f o = 2 MHz 3π/8 offset - 8PSK ITE research on SDR 23 UMTS SWR in ITE HW platforms digital radio reconfiguration design methodology collaborations conclusions Inter Filter 8 DDS DAC I Q sin cos Complex Mixer Decimating Filter 8 Decimating Filter 8 RF Out sin cos Complex Mixer ADC RF In Root Raised Cosine Root Raised Cosine 2Ç 2Ç Mapping QPSK Bits generation Inter Filter 8 2È 2È Decision QPSK BER Root Raised Cosine Root Raised Cosine DDS Polyphase Filter 32 Branches fbits = 1 Mbits/s fsymboles = 500 ksymboles/s over = 2 fsamples = 1 Msamples/s f ADC = 8 MHz f o = 2 MHz f DAC = 8 MHz IF = 10 MHz f o = 2 MHz fDAB = 4 fIF / 5 f0 = fDAC / 4 QPSK undersampling
  13. ITE research on SDR 24 • software radio in ITE

    • hardware platforms for experiments • digital radio on generic hardware • reconfiguration • design methodology perspectives • collaborations • conclusions ITE research on SDR 25 dynamic OTAR by SW download • real-time video link on a SWR EDGE standard • SW patch OTA download • SDR BTS – PC: reconfiguration manager & video server – SDR platform • SDR User Equipment – SDR platform supporting real-time reconfiguration without data stream interruption – PC for video display Reconfiguration manager SWR in ITE HW platforms digital radio reconfiguration design methodology collaborations conclusions User Equipment screen SDR BTS bi-directional radio channel TCP/IP TCP/IP SDR UE
  14. ITE research on SDR 26 system organization wired reconfiguration DSP

    0 Rx DSP 1 Ctrl DSP 2 Tx DSP 3 Not used Global RAM probes control link Pentek platform ADC DDC DUC DAC clk1 clk2 ethernet PC probe stream control link Matlab GUI PENTEK products PENTEK products Quad-DSP: 4 x C6201 Quad-DSP: 4 x C6201 Tx Tx: DUC + D/A : DUC + D/A Rx: A/D + DDC Rx: A/D + DDC Configuration manager (CMan) functions mapping of the application on the hardware SWR in ITE HW platforms digital radio reconfiguration design methodology collaborations conclusions AIR ITE research on SDR 27 application: EDGE modem (2.75G) DUC DAC pulse shaping -3π/8 offset analog digital IF I/Q EDGE mapping (8-psk) bits AD, DDC polyphase filter ↓ -3π/8 offset carrier phase correction phase estimation sync. decision (cordic) timing quality filter selection filter selection filter bank coefficients filter bank coefficients analog digital IF bits sampling alignment ε FIR branch I/Q Filter selection function selects the right polyphase interpolating filter branch given a timing error estimation ε. This mechanism enables sub-sample timing recovery. Filter selection function selects the right polyphase interpolating filter branch given a timing error estimation ε. This mechanism enables sub-sample timing recovery. Reconfigurable Rx software components code & parameters EDGE modulation : 3pi/8 offset 8-PSK Pulse shaping : Gaussian form Required Performance: 270 Ksymbols/s Obtained Performance : 291 Ksymbols/s SWR in ITE HW platforms digital radio reconfiguration design methodology collaborations conclusions
  15. ITE research on SDR 28 high-level view of the system

    organization • it can scale to support various operation schemes – network independent device reconfiguration – network controlled/managed reconfiguration • configuration data stored either locally or remotely • decision process under the device responsibility or under network responsibility based on the collection of relevant measurement data reconfigurable device network TxChEst Ch. Estim Local Remote A/D stage RF stage CMan Config. Manager HW Interfaces T x - R x DSP Transceiver higher layers ctrl I/F I/F I/F software hardware Active Config. Config. command I/F CStore Config. Store Local Remote SWR in ITE HW platforms digital radio reconfiguration design methodology collaborations conclusions ITE research on SDR 29 network reconfiguration management GUI SWR in ITE HW platforms digital radio reconfiguration design methodology collaborations conclusions Bug in the Timing Recovery sub-system Bug corrected by selective code change, i.e. Module 0 batch batch interactive in 3 steps interactive in 3 steps 1 1 2 2 3 3 rollback no noise sampling clock freq. drift
  16. ITE research on SDR 30 Rx Network Reconfiguration Manager UE

    Screen SDR UE transceiver SDR BTS transceiver Tx Rx Tx downlink uplink VIDEO APPLICATION Video service order of the user 2 - launch a video server 3 - send the video stream to the BTS 4 - conversion of the stream to the reconfigurable EDGE protocol stack 5 - EDGE Tx 6 - EDGE Rx 7 - identification of the service 8 - video stream is displayed on the screen Video DB Ctrl TCP/IP 1 - the network has a video database user's order video data stream ITE research on SDR 31 RECONFIGURATION at run-time patch download Rx Ctrl TCP/IP Tx Tx - bug only visible in certain circumstances - covery limit necessitating new processing - changes in the environment Network reconfiguration manager 1 - monitors a SDR UE 2 - detects some dysfunction 3 - identifies the problem 4 - finds the corresponding patch in its patch database 7 - install reconfiguration data in the UE's Rx internal memory 8 - activate the patch 9 - possibly: undo the operation if any problem Error DB patch DB probes Rx Ctrl 5 - download the patch to the UE included in the data stream 6 - separate video from reconfiguration data Network Reconfiguration Manager UE Screen SDR UE transceiver SDR BTS transceiver downlink uplink
  17. ITE research on SDR 32 SW download for bug fixing

    and performance enhancement SWR in ITE HW platforms digital radio reconfiguration design methodology collaborations conclusions Mobile Station screen DDC TCP/IP Configuration manager station TCP/IP control link & probes data stream uplink IF radio channel data control Global RAM DUC video stream, web pages from Rx Tx stream (data & control) EDGE modulator Glob. mem Tx EDGE protocol Rem. ctrl Glob. mem proxy ctrl web requests to Tx EDGE demodulator Rx downlink IF radio channel Rx stream (data & control) DDC Global RAM Tx stream (data & control) EDGE protocol proxy ctrl EDGE demodulator Rx Rx stream (data & control) Tx EDGE modulator DUC SW patch path Glob. mem Glob. mem Mobile station Base station Plug'n'Play probes Plug'n'Play probes Glob. mem Plug'n'Play Plug'n'Play ITE research on SDR 33 business case for real-time reconfiguration SWR in ITE HW platforms digital radio reconfiguration design methodology collaborations conclusions • manufacturer – bug fixing – upgrade capabilities • service provider – bug fixing – performance enhancement – cell capacity optimization (transmit power adaptation) • user may benefit in a transparent manner from – battery optimization – real-time quality of service management • standardization and regulation are needed!
  18. ITE research on SDR 34 • software radio in ITE

    • hardware platforms for experiments • digital radio on generic hardware • reconfiguration • design methodology perspectives • collaborations • conclusions ITE research on SDR 35 HW/SW co-design DSP and FPGA • SWR systems will not only contain processors – today's situation: HW accelerator for highest speed processing – medium term: radio applications will be more and more demanding, even if processing power increases • facing co-design is mandatory • SynDEx for heterogeneous multi-processing – INRIA CAD tool (INRIA: French national research lab in computer sciences) – in cooperation with IETR - INSA • image processing lab • telecom lab – Thesis of Mickaël RAULET (3rd year) - memory optimisation SWR in ITE HW platforms digital radio reconfiguration design methodology collaborations conclusions
  19. ITE research on SDR 36 SynDEx for multiprocessing and heterogeneity

    SynDEx entry • mono-processor version of the code • description of the algorithm (graph) • description of the HW architecture (graph) SynDEx job • partitioning, scheduling and timing prediction – optimized mapping of the algorithms on the HW architecture (heurisitic) – taking into account both algo execution time and communication delays • guaranteed functional accuracy with the mono-proc. version • automatic code generation • implementation on the target is so fast that verification may be considered in the scope of SynDEx SWR in ITE HW platforms digital radio reconfiguration design methodology collaborations conclusions ITE research on SDR 37 SynDEx • HW graph – input • SW application graph – input • timing graph after partitioning and scheduling – output execution parallelism automatic code generation SWR in ITE HW platforms digital radio reconfiguration design methodology collaborations conclusions SynDEx - graphically Example for a UMTS FDD TX Tx time of 1 UMTS FDD slot
  20. ITE research on SDR 38 implementations with SynDEx UMTS FDD

    uplink modulator / demodulator (Tx: 160 blocs - Rx: 240 blocs) • multi-DSP, FPGA - via FIFO • multi-GPP - via TCP • multi-DSP, multi-GPP - via TCP between the platform and the PC Tx Rx SWR in ITE HW platforms digital radio reconfiguration design methodology collaborations conclusions PSH 5120 2560 SCR 2560 2560 38400 SPRctrl 10 10 2560 SUM 2560 2560 2560 CST_SCR_code SPRdata 80 1200 2560 2560 DPCCH INT2 1200 1200 slot/slot frame/frame INT1 EQU 1200 1200 COD 1200 1200 SEG 1200 1200 CRC 1200 300 SRC 292 292 transport bloc MFL 5120 5120 RAKE 2560 5120 38400 DSPRctrl 10 10 2560 DSCR 2560 2560 2560 CST_SCR_code DSPRdata 80 1200 2560 2560 DPCCH DINT2 1200 1200 slot/slot frame/frame DINT1 DEQU DCOD DSEG DCRC 300 TEB 292 292 transport bloc 1200 1200 1200 1200 1200 1200 1200 ITE research on SDR 39 MPEG-4 over UMTS SWR in ITE HW platforms digital radio reconfiguration design methodology collaborations conclusions UMTS Demodulation Mpeg4 Coder UMTS Modulation Mpeg4 Decoder TCP PC PC TCP DSP DSP FIFO
  21. ITE research on SDR 40 SynDEx evolution In close relationship

    with Yves SOREL from INRIA Rocquencourt SynDEx needs to be extended for SWR • only time optimization on both processing and communications • only one processing element by FPGA Future work • memory: combined optimization with time – data buffer re-organization on each processor (at code generation phase) – repartition taking into account time and memory (in the heuristic) – thesis of Mickaël RAULET with IETR/INSA • FPGA – for parallel multi-processing in the same FPGA (with INSA/IETR) SWR in ITE HW platforms digital radio reconfiguration design methodology collaborations conclusions ITE research on SDR 41 • software radio in ITE • hardware platforms for experiments • digital radio on generic hardware • reconfiguration • design methodology perspectives • collaborations • conclusions
  22. ITE research on SDR 42 RNRT A3S • Adéquation Architecture

    / application Système – Thales Comm., Softeam, Lester (Université de Bretagne Sud - Lorient) • Goals – SDR system verification before platform implementation taking into account the SW repartition on the HW • 2 UML graphs (UML 1.4) and A3S profile – activity diagram for functional description of the SW application - SW graph – deployment diagram for HW platform - HW graph first step of verifications (connections…) • generates a XMI file • verification toolbox – scheduling and execution time – memory allocation – communication media overload either integrated in the UML tool or by web-service SWR in ITE HW platforms digital radio reconfiguration design methodology collaborations conclusions ITE research on SDR 43 A3S hardwre graph SWR in ITE HW platforms digital radio reconfiguration design methodology collaborations conclusions 6250: :FPGA_B:a3s-FPGA :FPGA_A:a3s-FPGA 4292: :DSP_A:a3s-DSP :DSP_C:a3s-DSP :FIFO_AC:a3s-FIFO :IOPortData1: :IOPortData1: RF: :ANT:a3s-ANT VIMinterfaceA: :FIFO_VIM:a3s-FIFO :FPGA_B:a3s-FPGA :FPGA_A:a3s-FPGA :FIFO_VIM:a3s-FIFO VIMinterfaceC: :FIFO_VIM:a3s-FIFO 6229: :DUC:a3s-DUC :DAC:a3s-DAC :PA:a3s-PA :AF:a3s-AF :DUC:a3s-DUC :DSP_A:a3s-DSP :DSP_C:a3s-DSP :FIFO_AC:a3s-FIFO :IOPortData1: :IOPortData1: :DAC:a3s-DAC :PA:a3s-PA :AF:a3s-AF :ANT:a3s-ANT :FIFO_VIM:a3s-FIFO with associated HW-related characteristics ⇒ HW-related verifications
  23. ITE research on SDR 44 A3S application graph- UMTS Tx

    SWR in ITE HW platforms digital radio reconfiguration design methodology collaborations conclusions FrameProcessing TransportBloc INT2 INT1 EQU COD SEG CST_SCR CRC SlotProcessing PSH SCR SUM SPRdpdch SPRdpcch DPCCHctrl RadioProcessing BBIF DAC PAT TAF ANT SUM SPRdpcch ANT SPRdpdch DPCCHctrl TransportBloc INT2 INT1 EQU COD SEG CST_SCR CRC PSH SCR BBIF DAC PAT TAF with associated implementation-related characteristics ⇒ application-related verifications ITE research on SDR 45 A3S application graph- UMTS Rx SWR in ITE HW platforms digital radio reconfiguration design methodology collaborations conclusions SlotProcessing MFL RAKE DSCR DSPR RAK_MM RAK_fin FrameProcessing DINT2 DINT1 DEQU DCOD DSEG TransportBloc CST_SCR_init DCRC CST_SCR_init RadioProcessing ANT RAF LNA ADC IFBB DSCR ANT DSPR DINT2 DINT1 DEQU DCOD DSEG TransportBloc DCRC MFL RAKE RAF LNA ADC IFBB RAK_MM RAK_fin
  24. ITE research on SDR 46 ⇒ performance verifications A3S hardwre

    graph - UMTS Tx SWR in ITE HW platforms digital radio reconfiguration design methodology collaborations conclusions 6250: :FPGA_B:a3s-FPGA :FPGA_A:a3s-FPGA PSH:PULSE_SHAPING 4292: :DSP_A:a3s-DSP :DSP_C:a3s-DSP :FIFO_AC:a3s-FIFO :IOPortData1: DPCCHctrl:DPCCH_SLOT :IOPortData1: SPRdpcch:SPREADCC SUM:SUM_BIT SCR:SCRAMBLING INT2:INT_SND INT1:INT_FST SEG:SEG_BLK CRC:CRC_END COD:CH_COD EQU:EQU_FRAME SPRdpdch:SPREADING RF: :ANT:a3s-ANT VIMinterfaceA: :FIFO_VIM:a3s-FIFO :FPGA_B:a3s-FPGA :FPGA_A:a3s-FPGA :FIFO_VIM:a3s-FIFO PSH:PULSE_SHAPING VIMinterfaceC: :FIFO_VIM:a3s-FIFO 6229: :DUC:a3s-DUC :DAC:a3s-DAC :PA:a3s-PA :AF:a3s-AF DAC:DAC_AD PAT:PA_DBM TAF:AF_LPF BBIF:DUC_BBIF :DUC:a3s-DUC :DSP_A:a3s-DSP :DSP_C:a3s-DSP :FIFO_AC:a3s-FIFO :IOPortData1: DPCCHctrl:DPCCH_SLOT :IOPortData1: SPRdpcch:SPREADCC SUM:SUM_BIT SCR:SCRAMBLING INT2:INT_SND INT1:INT_FST SEG:SEG_BLK CRC:CRC_END COD:CH_COD EQU:EQU_FRAME SPRdpdch:SPREADING :DAC:a3s-DAC :PA:a3s-PA :AF:a3s-AF :ANT:a3s-ANT DAC:DAC_AD PAT:PA_DBM TAF:AF_LPF :FIFO_VIM:a3s-FIFO BBIF:DUC_BBIF combined HW/SW characteristics ⇒ XMI file ITE research on SDR 47 IST E²R • End-to-End Reconfigurability • IP project: 28 partners - 8.9 M€ • Some of the partners: • Motorola, Siemens, Thales, Nokia, Mitsubishi, Panasonic, Alcatel, NTT DoCoMo, FTR&D, UoAthens, UoSurrey, King’s College • Work packages – WP1: System Research • technical, business and regulatory global approach across all WPs – WP2: Equipment Management • reconfiguration capabilities of equipments (terminal and BTS) – WP3: Network Support for Reconfiguration • network management for reconfiguring terminals and network entities – WP4: Radio Modem Reconfigurability • local configuration control and mechanisms for reliable reconfiguration – WP5: Evolution of Radio Resource and Spectrum Management • cognitive radio, network-oriented perspectives, spectrum control – WP6: E²R Proof of Concept Evolutionary Environment • demonstrator – WP7: dissemination – WP0: administrative SWR in ITE HW platforms digital radio reconfiguration design methodology collaborations conclusions
  25. ITE research on SDR 48 • software radio in ITE

    • hardware platforms for experiments • digital radio on generic hardware • reconfiguration • design methodology perspectives • collaborations • conclusions ITE research on SDR 49 conclusions • software radio research is a very wide research area – necessity to find synergies with partners – merge complementary results • industrial point of view – implementation is necessary – but not always sufficient • 2G - 2.5G - 3G radio on flexible platforms • SW component-based architecture for Over-the-air SW download • high-level heterogeneous co-design (more and more automatic) • not only for software radio but for other fields: image processing, automotive SWR in ITE HW platforms digital radio reconfiguration design methodology collaborations conclusions