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Adrien Thierry - Reconfiguration Partielle dyna...

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July 02, 2015
Research
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Adrien Thierry - Reconfiguration Partielle dynamique des FPGA pour les Applications Spatiales

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SCEE Team

July 02, 2015

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Transcript

  1. RePAS Reconfiguration Partielle dynamique des FPGA pour les Applications Spatiales

  2. Plan • Contexte • Principe de RePAS • Architecture du

    système • Démo • Bilan • Questions

  3. Contexte

  4. None
  5. None
  6. None

  7. Circuits physiquement renforcés CHERS ! VIEU X !

  8. Visite à Élancourt au printemps

  9. FPGA Moins chers Possibilité de reconfigurer le satellite à distance

    Mais plus sensibles aux radiations !
  10. None

  11. Utiliser les faiblesses des FPGA pour corriger les faiblesses des

    FPGA

  12. Projet de nano-satellite de l'association Supsat

  13. Structure d'un FPGA

  14. 1) Modification de la valeur d'un registre

  15. 2) Modification de la matrice de routage

  16. 3) Destruction d'une zone du FPGA

  17. Principe de RePAS

  18. Triplement de la fonction à protéger

  19. None

  20. Resynchronisation

  21. Problème résolu !

  22. Correction des erreurs du 2ème type

  23. Une zone est déconfigurée

  24. Reconfiguration partielle

  25. Lecture d'un bitstream partiel

  26. Lecture d'un bitstream partiel

  27. Problème résolu !

  28. Port ICAP accessible grâce au circuit ICAPE2

  29. Instanciation de l'ICAPE2 en VHDL

  30. Correction des erreurs du 3ème type

  31. Destruction d'une zone

  32. Zone détruite

  33. Activation d'une zone de secours

  34. Multiplexeurs pour la relocalisation de la zone défaillante

  35. Architecture du système

  36. Historique du projet

  37. L'année dernière

  38. Refonte complète de l'architecture

  39. None

  40. Automate de correction d'erreurs

  41. Stockage d'un bitstream dans la mémoire Lecture d'un bitstream

  42. None

  43. DEMO time !

  44. Liaison USB Carte de développement Nexys 4 (avec un Artix

    7) PC

  45. Bilan • Système qui corrige les 3 types d'erreurs •

    Système qui occupe une place réduite sur le FPGA • Terrain préparé pour la communication avec le reste du satellite

  46. Des questions ?